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PDF ST2226A Data sheet ( Hoja de datos )
| Número de pieza | ST2226A | |
| Descripción | PWM-Controlled Constant Current Driver | |
| Fabricantes | SiTi | |
| Logotipo |  |
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ST2226A
Version
Issue Date
File Name
Total Pages
: A.010
: 2004/04/12
: SP-ST2226A-A.010.doc
: 23
PWM-Controlled Constant Current Driver for LED
Displays
新竹市科學園區展業一路 9 號 7 樓之 1
SILICON TOUCH TECHNOLOGY INC.
9-7F-1, Prosperity Road I, Science Based Industrial Pard,
Hsin-Chu, Taiwan 300, R.O.C
Tel：886-3-5645656 Fax：886-3-5645626
1 page  
www.DataSheet4U.com
點晶科技股份有限公司
SILICON TOUCH TECHNOLOGY INC.
Pin Connection (QFN32 Bottom View)
ST2226A
DOUT
GND
IOUT15
IOUT14
IOUT13
IOUT12
IOUT11
IOUT10
25 26 27 28 29 30 31 32
24 1
23 2
22 3
21
Thermal PAD
20
4
5
19 6
18 7
17 8
16 15 14 13 12 11 10 9
DIN
VDD
IOUT0
IOUT1
IOUT2
IOUT3
IOUT4
IOUT5
Pin Assignment (QFN32)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
NAME
DIN
VDD
IOUT0
IOUT1
IOUT2
IOUT3
IOUT4
IOUT5
IOUT6
IOUT7
IGND
Pin No.
12
13
14
15
16
17
18
19
20
21
22
NAME
IGND
IGND
IGND
IOUT8
IOUT9
IOUT10
IOUT11
IOUT12
IOUT13
IOUT14
IOUT15
Pin No.
23
24
25
26
27
28
29
30
31
32
Thermal PAD
NAME
GND
DOUT
GCLK
DCLK
REXT
IGND
IGND
CMD[2]
CMD[1]
CMD[0]
IGND
ST2226A
Version：A.010
Page：4
5 Page 
www.DataSheet4U.com
點晶科技股份有限公司
SILICON TOUCH TECHNOLOGY INC.
ST2226A
2) LED Emitting Time and Current
ST2226A adjusts the LED luminance using PWM (pulse width modulation) technique.
The luminance data (DV) has a resolution of 10 bits (1024steps) and can be set
independently for each LED. The relationship between Iout, luminance data, and emitting
time is shown in Figure 2.
Current
DV x TGCLK
Iout
2 x GCLK
1024 x TGCLK
Time
“LED Emitting” command issued
Figure 2. PWM Current Output
3) Phase Relationship of DCLK and GCLK
Matching ST2226A’s GCLK and DCLK is an important step in the system design. If
there is a certain length of delay between the rising edge of DCLK and of GCLK, the
command “LED Emitting“& “LED Disable” will not be correctly recognized, which will then
cause the display data loss. It is safe to keep both of GCLK and DCLK rising at the same
time, so that the frequencies of DCLK and GCLK have an integer multiple relationship.
For the design which has a fixed, corresponding clock phase relationship between
GCLK & DCLK, e.g. the display controller is built by FPGAs, this clock phase problem is
unlikely to happen. However, if it dose happen, try to control the clock phase, e.g. invert
GCLK, to solve this problem. On the contrary, for the design which can not control the
clock phase, e.g. the display controller is built by microprocessors, the following sequential
modification on “Emitting” & “Disable” commands is preferred to be employed in the
design:
1. Gate GCLK.
2. Issue “Emitting” or “Disable” command.
3. Let go of GCLK.
ST2226A
Version：A.010
Page：10
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet ST2226A.PDF ] | |
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