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PDF VRS51L3074 Data sheet ( Hoja de datos )
| Número de pieza | VRS51L3074 | |
| Descripción | FRAM-enhanced high performance 8051-based microcontroller coupled | |
| Fabricantes | Ramtron Corporation | |
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VRS51L3074
9 SPI Interface
The SPI interface of the VRS51L3074’s provides
numerous enhancements compared to other vendor
offerings. The SPI interface’s key features include:
• Supports four standard SPI modes (clock
phase/polarity)
• Operates in master and slave modes
• Automatic control of up to four chip select lines
• Configurable transaction size (1 to 32 bits)
• Transaction size of >32 bits is possible
• Double Rx and TX data buffers
• Configurable MSB or LSB first transaction
• Generation frame select/load signals
FIGURE 14: SPI INTERFACE OVERVIEW
Before the SPI can be accessed it must first be
enabled by setting the SPIEN bit of the PERIPHEN1
register to 1.
9.1 SPI Control Registers
The SPICTRL register controls the operating modes of
the SPI interface in master mode.
TABLE 97:SPI CONTROL REGISTER - SPICTRL SFR C1H
7 65 4 3 2
R/W
R/W
R/W
R/W
R/W
R/W
0 00 0 0
0
1
R/W
0
0
R/W
1
Bit Mnemonic Description
7 SPICLK[2:0] SPI Communication Speed (Master Mode)
000 = Sys Clk / 2 ( / 8 if SPISLOW = 1)
001 = Sys Clk / 4 ( / 16 if SPISLOW = 1)
010 = Sys Clk / 8 ( / 32 if SPISLOW = 1)
011 = Sys Clk / 16 ( / 64 if SPISLOW = 1)
100 = Sys Clk / 32 ( / 128 if SPISLOW = 1)
101 = Sys Clk / 64 ( / 256 if SPISLOW = 1)
110 = Sys Clk / 128 ( / 512 if SPISLOW = 1)
111 = Sys Clk / 256 ( / 1024 if SPISLOW = 1)
4
SPICS[1:0]
SPI Active Chip Select Line (Master Mode)
00 = CS0 is active
01 = CS1 is active
10 = CS2 is active
11 = CS3 is active
2
SPICLKPH
SPI Clock Phase
0 = SD0 output on rising edge and SDI
sampling on falling edge
1= SD0 output on falling edge and SDI sampling
on rising edge
1 SPICLKPOL SPI Clock Polarity
0 = SCK stays at 0 when SPI is inactive
1 = SCK stays at 1 when SPI is inactive
0 SPIMASTER SPI Master Mode Enable
0 = SPI operates in slave mode
1 = SPI operate in master mode (default)
When the SPIMASTER bit is set to 1, the SPI interface
operates in master mode. This is the default operating
mode of the VRS51L3074 SPI interface after reset.
9.2 Setting Up Clock Phase and Polarity
The clock phase and polarity is controlled by the
SPICLKPH and SPICLKPOL bits, respectively. The
following diagrams show the communication timing
associated with the clock phase and polarity.
SPI Mode 0:
FIGURE 15: SPI MODE 0
SPI MODE 0: SPICKPOL =0,SPICKPH =1 (Normal Mode Shown)
CSX
SCK
SDO
MSB
SDI
*Arrows indicate the edge where the data acquisition occurs
LSB
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VRS51L3074
9.9 Alternate CS3 functions
For external SPI devices which require the use of a
load or a frame select signal, the VRS51L3074 can be
configured to either generate an active low frame
select or active high load signal when operating in
master mode.
9.9.1 Frame Select signal on CS3
When the FONCS3 bit of the SPICONFIG register is
set to 1, the SPI interface will generate an active low
frame select pulse on the CS3 pin (see the following
timing diagram).
FIGURE 22: SPI FRAME SELECT PULSE TIMING
FRAME SELECT Pulse (SPI Mode 0 shown)
CS3
Frame Select Pulse width = 1 / Sys Clk
CSX
SCK
SDO
MSB
SDI
*Arrows indicate the edge where the data acquisition occurs
LSB
9.9.2 Load Signal on CS3
When the SPILOADCS3 bit of the SPICONFIG register
is set to 1 and the FSONCS3 bit is cleared, an active
low load signal will be generated on the CS3 line of the
SPI interface.
FIGURE 23: SPI LOAD PULSE TIMING
LOAD Pulse (SPI Mode 0 shown)
CS3
Load Pulse width = 1 / Sys Clk
CSX
SCK
SDO
MSB
SDI
*Arrows indicate the edge where the data acquisition occurs
LSB
Note that the frame select alternate function has
priority over the load function. This means that if the
FSONCS3 bit is set, the alternate function selected
will be the frame select, independent of the value of
the SPILOAD bit.
9.10 SPI Activity Monitoring
The ability to monitor the state of communication of the
SPI interface can be useful in highly modular
applications in which the SPI interface is handled by
interrupts. The SPISTATUS register contains two flags
that can be used to monitor the CS and SS signals of
the SPI interface.
The SPINOCS bit of the SPISTATUS register returns
the logical AND of all the SPI CS lines of the
VRS51L3074. If all the CS lines are inactive (logic
high), the SPI interface sets the SPINOCS to 1. The
SPINOCS bit is used to verify that the SPI interface is
idle before reconfiguring it or starting a new
transaction.
The SPINOCS bit of the SPISTATUS register is valid
four system clock cycles after the SPI transmission
begins. This delay is independent of the SPI
transaction speed.
As such, after a write operation to the SPIRXTX0
register, which will trigger a SPI transaction in master
mode, a NOP instruction (1 cycle) must be added
before the MOV Rn, SPISTATUS instruction (3
cycles).
The SSPINVAL bit of the SPISTATUS register returns
the logic level on the SS pin.
9.11 SPI TX Underrun Flag
The SPI interface provides an underrun condition flag
that can be used to flag whether the software has
failed to update transmission buffer in time for the next
transfer. This is especially useful when the SPI
interface is used to transmit packets greater than 32
bits in length.
If an underrun condition occurs, the SPIUNDERF bit of
the SPI status register will be set to 1. This bit can be
cleared by writing a 1 to the SPIUNDERC bit of the
SPICONFIG register.
Note that SPI underrun monitoring is not linked to any
of the SPI interrupts, therefore, this flag can only be v
manually by software
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VRS51L3074
VRS51L3074 operates as a peripheral in a host-
controlled system.
When in master mode, the I²C interface can be forced
to generate a start condition after the next data
acknowledge phase. This is done by setting the
I2CMASTART bit to 1.
When the MASTRARB bit is set to 1, communications
of the I²C will be monitored and an interrupt will be
generated if arbitration with slave devices on the bus is
lost. The interrupt flag associated with this process is
the I2CERROR bit of the I2CSTATUS register.
If the I2CRXSTOP bit is set to 1, the I²C interface will
not acknowledge after reception of the next byte, but
will generate a stop condition instead. This will, in
effect, end the transaction with the master device.
When the I²C interface is configured as a master and
the I2CSCLLOW bit of the I2CCONFIG register is set
to 1, the SCL line will be driven low during the next
data acknowledge phase. This feature enables the
user to add the equivalent of wait states to the transfer
in order to support “slow” devices connected to the I²C
bus.
The I²C interface includes support for four interrupt
conditions via two interrupt vectors.
• RX Data Available
• RX Overrun
• TX Empty
• Master lost arbitration
The following table summarizes the possible interrupt
sources at the I²C interface level.
TABLE 111: I²C INTERRUPT SOURCES
I²C Interrupt
I2CCONFIG bit
(Set to 1 to activate)
RX Data
Available
RX Overrun
I2CRXAVEN
I2CRXOVEN
TX Empty
I2CTXEEN
Master Lost
Arbitration
MASTRARB
Interrupt
Vector
4Bh
(Int 9)
0x4B
(Int 9)
0x4B
(Int 9)
0x53
(Int 10)
To activate the I²C interface interrupts, the
corresponding enable bit of the I2CCONFIG register
must be set to 1. This will allow the I²C interrupt to
propagate to the VRS51L3074’s interrupt controller. In
order for the I²C interrupt to be recognized by the
processor, the corresponding bit of the INTEN2 and
INTSRC2 registers must be configured accordingly.
www.ramtron.com
See the VRS51L3074 interrupt section for more
details.
10.4 I²C Timing Control Register
The I2CTIMING register controls the communication
speed when the I²C interface is configured in master
mode. When in slave mode, it defines the values of the
setup and hold times.
TABLE 112:I²C TIMING REGISTER - I2CTIMING SFR D2H
7 65 4 3 2
R/W
R/W
R/W
R/W
R/W
R/W
0 00 0 1
1
1
R/W
0
0
R/W
0
Bit Mnemonic Description
7:0 I2CTIMING[7:0] I²C master/slave timing configuration register
See Below
The following formulas demonstrate the impact of the
I2CTIMING value on the communication speed and
setup/hold times.
In master mode:
SCL period =
I2CCLK
32*( I2CTIMING[7:0] + 1)
The following table provides examples of the
I2CTIMING values and the corresponding
communication speed:
TABLE 113: I²C COMMUNICATION SPEED VS. I2CTIMING REGISTER VALUE (FOSC = 40MHZ)
I2CTIMING
00h
02h
0Ch (Reset)
7Ch
FFh
I2C Com Speed
1.25 MHz
416.77 kHz
96.15 kHz
10kHz
4.88kHz
In Slave Mode:
Set-up/Hold Time = I2CCLKperiod * I2CTIMING[7:0]
In this case, the precision is: 2 x I2CCLKperiod
TABLE 114: I²C SETUP AND HOLD TIME VS. I2CTIMING REGISTER VALUE (FOSC = 40MHZ)
I2CTIMING
00h
0Ch
FFh
Setup/Hold
Time
0 uS
0.3 uS
6.38 uS
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