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PDF STSR2P Data sheet ( Hoja de datos )
| Número de pieza | STSR2P | |
| Descripción | FORWARD SYNCHRONOUS RECTIFIERS SMART DRIVER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de STSR2P (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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STSR2P/
STSR2PM
FORWARD SYNCHRONOUS
RECTIFIERS SMART DRIVER
s SUPPLY VOLTAGE RANGE: 4.5V TO 5.5V
s TYPICAL PEAK OUTPUT CURRENT:
SOURCE -2A, SINK 3.5A
s OPERATING FREQUENCY: 20 TO 750 KHZ
s SMART TURN-OFF ANTICIPATION TIMING
s OPERATION INDEPENDENT FROM THE
FORWARD MAGNETIC RESET TECHNIQUE
s POSSIBILITY TO OPERATE IN
DISCONTINUOUS MODE
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DESCRIPTION
STSR2P Smart Driver IC provides two
complementary high current outputs to drive
Power Mosfets. The IC is dedicated to properly
drive secondary Synchronous Rectifiers in
medium power, low output voltage, high efficiency
Forward Converters. From a synchronizing clock
input, STSR2P generates two driving signals with
the self-setting of dead time between
complementary pulses. The IC operation prevents
secondary side shoot-through conditions
providing proper timing at the outputs turn-off
transition. This smart function operates through a
fast cycle-after-cycle control logic mechanism
based on an internal high frequency oscillator,
synchronized by the clock signal. A fixed
SO-8
anticipation in turning-off the OUTGATE1 with
respect to the clock signal transition is provided,
while the anticipation in turning off the OUTGATE2
can be set through external components. The
adopted transitions revelation mechanism makes
circuit operation independent by the forward
magnetic reset technique used, avoiding most of
the common problems inherent in self-driven
synchronous rectifiers. A special Inhibit function
allows the shut-off of OUTGATE2. This feature
makes discontinuous conduction mode possible
and prevents the freewheeling mosfet from
sinking current from the output.
STSR2P automatically turns off the outputs when
duty-cycle is lower than 13%, while STSR2PM
works even at very low duty-cycle values.
SCHEMATIC DIAGRAM
September 2003
CK 4
PEAK
DETECTOR
+
HIGH
FREQUENCY
OSCILLATOR
INHIBIT 5
-
+
25mV
Vcc
2
BIAS
UVLO
+
5.7V
ANTICIPATION
SET
+
DIGITAL OUTPUT
CONTROL BUFFERS
3 SETANT2
1 OUTGate1
7 OUTGate2
6
SGLGND
8
PWRGND
1/12
1 page  
TIMING DIAGRAM
STSR2P/STSR2PM
APPLICATION INFORMATION: STSR2 IN FORWARD CONVERTER SECONDARY SIDE
NOTES
1) Ceramic Capacitors C1 and C2 must be placed very close to the IC;
2) R1 and R2 set the anticipation time by partitioning the VCC voltage;
3) R3 and R4 is a resistor divider meant to provide the correct CK voltage range;
4) R5 limits the current flowing through diode D2 when Freewheeling drain voltage is high;
5) D1 could be necessary to protect INHIBIT pin from negative voltages.
6) D2 could be necessary to protect INHIBIT pin from voltages higher than VCC
7) D3 could be necessary to protect CK pin from voltages higher than VCC.
8) SGLGND layout trace must not include OUTGATE1,2 current paths.
9) A capacitor in parallel with R4 could be necessary to eliminate turn off voltage spike.
5/12
5 Page 
DIM.
A
C
D
N
T
Ao
Bo
Ko
Po
P
STSR2P/STSR2PM
Tape & Reel SO-8 MECHANICAL DATA
MIN.
12.8
20.2
60
8.1
5.5
2.1
3.9
7.9
mm.
TYP
MAX.
330
13.2
22.4
8.5
5.9
2.3
4.1
8.1
MIN.
0.504
0.795
2.362
0.319
0.216
0.082
0.153
0.311
inch
TYP.
MAX.
12.992
0.519
0.882
0.335
0.232
0.090
0.161
0.319
11/12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet STSR2P.PDF ] | |
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