PDF MC33596 Data sheet ( Hoja de datos )

Número de pieza	MC33596
Descripción	PLL Tuned UHF Receiver
Fabricantes	Motorola Semiconductors
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No Preview Available ! Freescale Semiconductor Data Sheet MC33596 Rev. 3, 06/2007 MC33596 PLL Tuned UHF Receiver for Data Transfer Applications 1 Overview The MC33596 is a highly integrated receiver designed for low-voltage applications. It includes a programmable PLL for multi-channel applications, an RSSI circuit, a strobe oscillator that periodically wakes up the receiver while a data manager checks the content of incoming messages. A configuration www.DataSheet4U.com switching feature allows automatic changing of the configuration between two programmable settings without the need of an MCU. LQFP32 2 Features General: • 304 MHz, 315 MHz, 426 MHz, 434 MHz, 868 MHz, and 915 MHz ISM bands • Choice of temperature ranges: — –40°C to +85°C — –20°C to +85°C • OOK and FSK reception • 20 kbps maximum data rate using Manchester coding • 2.1 V to 3.6 V or 5 V supply voltage • Programmable via SPI • 6 kHz PLL frequency step RSSIOUT VCC2RF RFIN GNDLNA VCC2VCO GND NC GND 1 2 3 4 5 6 7 8 QFN32 24 SEB 23 SCLK 22 MOSI 21 MISO 20 CONFB 19 DATACLK 18 RSSIC 17 GNDDIG © Freescale Semiconductor, Inc., 2006, 2007. All rights reserved. 1 page 4 Silicon Version This data sheet describes the functional features of silicon version ES4.1. Silicon Version 5 Maximum Ratings Table 2. Maximum Ratings Parameter Supply voltage on pin: VCCIN Supply voltage on pins: VCCINOUT, VCCDIG Supply voltage on pins: VCC2IN, VCC2RF, VCC2VCO Voltage allowed on each pin (except digital pins) Voltage allowed on digital pins: SEB, SCLK, MISO, MOSI, CONFB, DATACLK, RSSIC, STROBE ESD HBM voltage capability on each pin1 ESD MM voltage capability on each pin2 Solder heat resistance test (10 s) Storage temperature Junction temperature NOTES: 1 Human body model, AEC-Q100-002 rev. C. 2 Machine model, AEC-Q100-003 rev. C. Symbol VCCIN VCC VCC2 — VCCIO — — — TS TJ Value VGND–0.3 to 5.5 VGND–0.3 to 3.6 VGND–0.3 to 2.7 VGND–0.3 to VCC2 VGND–0.3 to VCCIN+0.3 ±2000 ±200 260 –65 to +150 150 Unit V V V V V V V °C °C °C Freescale Semiconductor MC33596 Data Sheet, Rev. 3 5 5 Page Register Access through SPI R/W specifies the type of operation: 0 = Read 1 = Write Thus, this bit is associated with the presence of information on MOSI (when writing) or MISO (when reading). Figure 4 and Figure 5 show write and read operations in a typical SPI transfer. In both cases, the SPI is a slave. A received byte is considered internally on the eighth falling edge of SCLK. Consequently, the last received bits, which do not form a complete byte, are lost. NOTE A low level applied to CONFB does not affect the configuration register contents. SEB CONFB SCLK (Input) MOSI (Input) MISO (Output) N1 N0 A4 A3 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Figure 4. Write Operation in Configuration Mode (N[1:0] = 01) SEB CONFB SCLK (Input) MOSI (Input) MISO (Output) N1 N0 A4 A3 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Figure 5. Read Operation in Configuration Mode (N[1:0] = 01) 10.3 Configuration Switching This feature allows for defining two different configurations using two different banks, and for switching them automatically during wakeup when using a strobe oscillator, or by means of the strobe pin actuation by the MCU. Freescale Semiconductor MC33596 Data Sheet, Rev. 3 11 11 Page

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