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PDF Si5321 Data sheet ( Hoja de datos )
| Número de pieza | Si5321 | |
| Descripción | SONET/SDH PRECISION CLOCK MULTIPLIER IC | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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Si5321
SONET/SDH PRECISION CLOCK MULTIPLIER IC
Features
Ultra-low jitter clock output with jitter Digital hold for loss-of-input clock
generation as low as 0.3 psRMS
Support for 255/238 (15/14),
No external components (other than a 255/237 (85/79), and 66/64 FEC scaling
resistor and bypassing)
(ITU-T G.709 and IEEE 802.3ae)
Input clock ranges at 19, 39, 78, 155, Selectable loop bandwidth
311, or 622 MHz
Loss-of-signal alarm output
Output clock ranges at 19, 39, 78, 155, Low power
311, 622, 1244, or 2488 MHz
Small size (9 x 9 mm)
Maximum range includes 693 MHz for Backwards compatible with Si5320
10 GbE FEC support
Applications
SONET/SDH line/port cards
Terabit routers
Core switches
Digital cross connects
Description
The Si5321 is a precision clock multiplier that exceeds the requirements of high-speed
communication systems, including OC-192/OC-48 and 10 Gigabit Ethernet. This device
phase locks to an input clock in the 19, 39, 78, 155, 311 or 622 MHz frequency range
and generates a frequency-multiplied clock output that can be configured for operation
in the 19, 39, 78, 155, 622, 1244, or 2488 MHz frequency range. Silicon Laboratories
DSPLL® technology provides PLL functionality with unparalleled performance. It
eliminates external loop filter components, provides programmable loop parameters,
and simplifies design. FEC rates are supported by selectable forward and reverse 255/
238 (15/14), 255/237 (85/79), and 66/64 (33/32) conversion factors. The ITU-T G.709
255/237 rate and the IEEE 802.3ae 66/64 rate are supported when using a 155 MHz or
higher rate input clock. The performance and integration of Silicon Laboratories’ Si5321
clock IC provides high-level support of the latest specifications and systems. It operates
from a single 3.3 V supply.
Functional Block Diagram
Si5321
Si5321
Ordering Information:
See page 30.
REXT
VSEL33
VDD
GND
FXDDELAY
CLKIN+
CLKIN–
VALTIME
LOS
Biasing & Supply Regulation
2 ÷ DSPLL®
Signal
Detect
3
2
2
÷
2
Calibration
CAL_ACTV
DH_ACTV
CLKOUT+
CLKOUT–
FRQSEL[2:0]
RSTN/CAL
BWBOOST
INFRQSEL[2:0] FEC[2:0]
BWSEL[1:0]
Rev. 2.5 8/08
Copyright © 2008 by Silicon Laboratories
Si5321
1 page  
CLKIN+
CLKIN–
Si5321
V IS
A. Operation with Single-Ended Clock Input*
Note: W hen using single-ended clock sources, the unused clock
input on the Si5321 m ust be ac-coupled to ground.
C L K IN +
C L K IN –
(CLKIN+) – (CLKIN–)
0.5 VID
V ID
B. Operation with Differential Clock Input
Note: Transm ission line term ination, when required, m ust be provided
externally.
Figure 1. CLKIN Voltage Characteristics
80%
20%
tF tR
Figure 2. Rise/Fall Time Measurement
(C LKIN+) - (C LKIN - )
tL O S
0V
Figure 3. Transitionless Period on CLKIN for Detecting a LOS Condition
Rev. 2.5
5
5 Page 
Si5321
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Wander/Jitter at 1600 Hz Bandwidth
(BWSEL[1:0] = 01 and BWBOOST = 0; FXDDELAY = 1)
Jitter Tolerance (see Figure 9)
JTOL(PP)
f = 16 Hz
f = 160 Hz
1000
100
—
—
— ns
— ns
f = 1600 Hz
10 — — ns
CLKOUT RMS Jitter Generation
FEC[2:0] = 000
JGEN(RMS)
12 kHz to 20 MHz
50 kHz to 80 MHz
— 0.8 1.2 ps
— 0.27 0.35 ps
CLKOUT RMS Jitter Generation
JGEN(RMS)
FEC[2:0] = 001, 010, 100, 101, 110, 111
12 kHz to 20 MHz,
50 kHz to 80 MHz,
— 0.9 1.2 ps
— 0.27 0.35 ps
CLKOUT Peak-Peak Jitter Generation
FEC[2:0] = 000
JGEN(PP)
12 kHz to 20 MHz,
50 kHz to 80 MHz,
— 6.7 10.0 ps
— 3.0 5.0 ps
CLKOUT Peak-Peak Jitter Generation JGEN(PP)
FEC[2:0] = 001, 010, 100, 101, 110, 111
12 kHz to 20 MHz,
50 kHz to 80 MHz,
— 6.5 10.0 ps
— 3.0 5.0 ps
Jitter Transfer Bandwidth (see Figure 6)
FBW
Wander/Jitter Transfer Peaking
JP
Wander/Jitter at 3200 Hz Bandwidth
(BWSEL[1:0] = 01 and BWBOOST = 1; FXDDELAY = 1)
BW = 1600 Hz
< 1600 Hz
— 1600 — Hz
— 0.0 0.1 dB
Jitter Tolerance (see figure 7)
f = 32 Hz
500 — — ns
f = 320 Hz
50 — — ns
f = 3200 Hz
5 — — ns
CLKOUT RMS Jitter Generation
FEC[2:0] = 000
JGEN(RMS)
12 kHz to 20 MHz,
50 kHz to 80 MHz,
— 0.8 1.0 ps
— 0.25 0.3 ps
CLKOUT Peak-Peak Jitter Generation
FEC[2:0] = 000
JGEN(PP)
12 kHz to 20 MHz,
50 kHz to 80 MHz,
— 6.1 10.0 ps
— 3.0 5.0 ps
Jitter Transfer Bandwidth (see Figure 6)
FBW
BW = 3200 Hz
— 3200 — Hz
Notes:
1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2. For reliable device operation, temperature gradients should be limited to 10 °C/min.
3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms
of nanoseconds per millisecond. The equivalent ps/s unit is used here since the maximum phase transient magnitude
for the Si5321 (tPT_MTIE) never reaches one nanosecond.
Rev. 2.5
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet Si5321.PDF ] | |
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