PDF SI5320 Data sheet ( Hoja de datos )

Número de pieza	SI5320
Descripción	SONET/SDH PRECISION CLOCK MULTIPLIER IC
Fabricantes	Silicon Laboratories
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No Preview Available ! Si5320 SONET/SDH PRECISION CLOCK MULTIPLIER IC Features  Ultra-low-jitter clock output with jitter generation as low as 0.3 psRMS  No external components (other than a resistor and standard bypassing)  Input clock ranges at 19, 39, 78, 155, 311, and 622 MHz  Output clock ranges at 19, 155, or 622 MHz  Digital hold for loss of input clock  Support for forward and reverse FEC clock scaling  Selectable loop bandwidth  Loss-of-signal alarm output  Low power  Small size (9x9 mm) Applications  SONET/SDH line/port cards  Optical modules  Core switches  Digital cross connects  Terabit routers Description The Si5320 is a precision clock multiplier designed to exceed the requirements of high-speed communication systems, including OC-192/OC-48 and 10 GbE. This device phase locks to an input clock in the 19, 39, 78, 155, 311, or 622 MHz frequency range and generates a frequency-multiplied clock output that can be configured for operation in the 19, 155, or 622 MHz range. Silicon Laboratories’ DSPLL™ technology delivers all PLL functionality with unparalleled performance while eliminating external loop filter components, providing programmable loop parameters, and simplifying design. FEC rates are supported with selectable 255/ 238 or 238/255 scaling of the clock multiplication ratios. The Si5320 establishes a new standard in performance and integration for ultra-low-jitter clock generation. It operates from a single 3.3 V supply. Functional Block Diagram REXT VSEL33 VDD GND FXDDELAY CLKIN+ CLKIN– VALTIME LOS Biasing & Supply Regulation 2 Signal Detect ÷ 3 DSPLLTM 22 ÷ 2 Calibration CAL_ACTV DH_ACTV CLKOUT+ CLKOUT– FRQSEL[1:0] RSTN/CAL INFRQSEL[2:0] FEC[1:0] DBLBW BWSEL[1:0] Si5320 Si5320 Ordering Information: See page 29. Rev. 2.5 8/08 Copyright © 2008 by Silicon Laboratories Si5320 1 page CLKIN+ CLKIN– Si5320 V IS A. Operation with Single-Ended Clock Input Note: W hen using single-ended clock sources, the unused clock input on the Si5320 m ust be ac-coupled to ground. C L K IN + C L K IN – (CLKIN+) – (CLKIN–) 0.5 VID V ID B. Operation with Differential Clock Input Note: Transm ission line term ination, when required, m ust be provided externally. Figure 1. CLKIN Voltage Characteristics 80% 20% tF tR Figure 2. Rise/Fall Time Measurement (C L K IN + ) – (C L K IN – ) 0V tL O S Figure 3. Transitionless Period on CLKIN for Detecting a LOS Condition Rev. 2.5 5 5 Page Si5320 Table 4. AC Characteristics (PLL Performance Characteristics) (Continued) (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 00 JGEN(PP) 12 kHz to 20 MHz 50 kHz to 80 MHz — 6.8 10.0 ps — 3.7 5.0 ps Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking Wander/Jitter at 3200 Hz Bandwidth (BWSEL[1:0] = 00 and DBLBW = 0) FBW BW = 3200 Hz — 3200 — Hz JP < 3200 Hz — 0.05 0.1 dB Jitter Tolerance (see Figure 7) JTOL(PP) f = 32 Hz f = 320 Hz 1000 — 100 — — ns — ns f = 3200 Hz 10 — — ns CLKOUT RMS Jitter Generation FEC[1:0] = 00 JGEN(RMS) 12 kHz to 20 MHz 50 kHz to 80 MHz — 0.86 1.2 ps — 0.29 0.4 ps CLKOUT RMS Jitter Generation FEC[1:0] = 01, 10 JGEN(RMS) 12 kHz to 20 MHz 50 kHz to 80 MHz — 0.79 1.2 ps — 0.28 0.4 ps CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 00 JGEN(PP) 12 kHz to 20 MHz 50 kHz to 80 MHz — 7.7 10.0 ps — 3.9 5.0 ps CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 01, 10 JGEN(PP) 12 kHz to 20 MHz 50 kHz to 80 MHz — 7.2 10.0 ps — 4.0 5.0 ps Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking Wander/Jitter at 6400 Hz Bandwidth (BWSEL[1:0] = 00 and DBLBW = 1) FBW BW = 3200 Hz — 3200 — Hz JP < 3200 Hz — 0.05 0.1 dB Jitter Tolerance (see Figure 7) f = 64 Hz 500 — — ns f = 640 Hz 50 — — ns f = 6400 Hz 5 — — ns CLKOUT RMS Jitter Generation FEC[1:0] = 00 JGEN(RMS) 12 kHz to 20 MHz 50 kHz to 80 MHz — 0.7 1.0 ps — 0.25 0.3 ps CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 00 JGEN(PP) 12 kHz to 20 MHz 50 kHz to 80 MHz — 6.6 9.0 ps — 3.8 5.0 ps Notes: 1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient. 2. For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/s unit is used here since the maximum phase transient magnitude for the Si5320 (tPT_MTIE) never reaches one nanosecond. Rev. 2.5 11 11 Page

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