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PDF VND5025LAK-E Data sheet ( Hoja de datos )
| Número de pieza | VND5025LAK-E | |
| Descripción | Double channel high side driver | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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VND5025LAK-E
Double channel high side driver with analog
current sense for automotive applications
Features
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Max supply voltage
Operating voltage range
Max on-state resistance (per ch.)
Current limitation (typ)
Off state supply current
VCC 41V
VCC 4.5 to 36V
RON 25mΩ
ILIMH
IS
60A
2µA(1)
1. Typical value with all loads connected
■ Features
– In-rush current active management by
power limitation
– Very low stand-by current
– 3.0V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC
European directive
– Package: ECOPACK®
■ Diagnostic functions
– Proportional load current sense
– High current sense precision for wide range
currents
– Current sense disable
– Thermal shutdown indication
– Very low current sense leakage
■ Protection
– Undervoltage shut-down
– Overvoltage clamp
– Load current limitation
– Self-limiting of fast thermal transients
– Protection against loss of ground and loss
of VCC
PowerSSO-24™
– Thermal shut down
– Reverse battery protection(a)
– Electrostatic discharge protection
Description
The VND5025LAK-E is a monolithic device made
using STMicroelectronics VIPower M0-5
technology, intended for driving resistive or
inductive loads with one side connected to
ground, and suitable for driving LEDs.
Active VCC pin voltage clamp protects the device
against low energy spikes (see ISO7637 transient
compatibility table).
This device integrates an analog current sense
which delivers a current proportional to the load
current (according to a known ratio) when
CS_DIS is driven low or left open.
When CS_DIS is driven high, the CURRENT
SENSE pin is in a high impedance condition.
Output current limitation protects the device in
overload condition. In case of long overload
duration, the device limits the dissipated power to
safe level up to thermal shut-down intervention.
Thermal shut-down with automatic restart allows
the device to recover normal operation as soon as
fault condition disappears.
Table 1. Order codes
Package
PowerSSO-24™
a. See Figure 26: Application schematic
Tube
VND5025LAK-E
Tape and Reel
VND5025LAKTR-E
March 2007
Rev 3
1/31
www.st.com
1
1 page  
VND5025LAK-E
Block diagram and pin description
1 Block diagram and pin description
Figure 1. Block diagram
GND
INPUT1
INPUT2
VCC
CLAMP
LOGIC
UNDERVOLTAGE
PwCLAMP 1
DRIVER 1
ILIM 1
PwrLIM 1
VDSLIM 1
OVERTEMP. 1
IOUT1
K1
CS_DIS
PwrLIM 2
PwCLAMP 2
DRIVER 2
ILIM 2
VDSLIM 2
OVERTEMP. 2
IOUT2
K2
OUTPUT1
CURRENT
SENSE1
OUTPUT2
CURRENT
SENSE2
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Table 2. Pin functions
Name
Function
VCC
OUTPUT1,2
GND
Battery connection
Power output
Ground connection; must be reverse battery protected by an external
diode/resistor network
INPUT1,2
CURRENT SENSE1,2
CS_DIS
Voltage controlled input pin with hysteresis, CMOS compatible; controls
output switch state
Analog current sense pin; delivers a current proportional to the load
current
Active high CMOS compatible pin to disable the current sense pin
Figure 2.
Configuration diagram (top view) and suggested connections for unused
and N.C. pins
VCC
GND
N.C.
INPUT2
N.C.
INPUT1
N.C.
CURRENT SENSE1
N.C.
CURRENT SENSE2
CS_DIS.
VCC
1
2
3
4
5
6
7
8
9
10
11
12
24 OUTPUT2
23 OUTPUT2
22 OUTPUT2
21 OUTPUT2
20 OUTPUT2
19 OUTPUT2
18 OUTPUT1
17 OUTPUT1
16 OUTPUT1
15 OUTPUT1
14 OUTPUT1
13 OUTPUT1
Connection / Pin Current Sense
N.C.
TAB = VCC
Output
Input
CS_DIS
Floating
N.R.
XX
X
X
To Ground
1kΩ resistor X N.R. 10kΩ resistor
N.R. = Not recommended
10kΩ resistor
5/31
5 Page 
VND5025LAK-E
Electrical characteristics
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Table 9. Current sense (8V < VCC < 16V) (continued)
Symbol
Parameter
Test conditions
tDSENSE1H
Delay response
time from falling
edge of CS_DIS
pin
VSENSE < 4V, 0.5 < IOUT < 10A
ISENSE = 90% of ISENSEMAX (see
Figure 4)
tDSENSE1L
Delay response
time from rising
edge of CS_DIS
pin
VSENSE < 4V, 0.5 < IOUT < 10A
ISENSE = 10% of ISENSEMAX (see
Figure 4)
tDSENSE2H
Delay response
time from rising
edge of INPUT
pin
VSENSE < 4V, 0.5 < IOUT < 10A
ISENSE = 90% of ISENSEMAX (see
Figure 4)
∆tDSENSE2H
Delay response
time between
rising edge of
output current
and rising edge
of current sense
VSENSE < 4V,
ISENSE = 90% of ISENSEMAX,
IOUT = 90% of IOUTMAX, IOUTMAX = 3A
(see Figure 5)
tDSENSE2L
Delay response
time from falling
edge of INPUT
pin
VSENSE < 4V, 0.5 < IOUT < 10A
ISENSE = 10% of ISENSEMAX (see
Figure 4)
1. Parameter guaranteed by design; it is not tested.
Min Typ Max Unit
50 100
5 20
70 300
µs
110
100 250
Figure 4. Current sense delay characteristics
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
tDSENSE2H
tDSENSE1L
tDSENSE1H
tDSENSE2L
11/31
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