|
|
PDF MT5C1008LL Data sheet ( Hoja de datos )
| Número de pieza | MT5C1008LL | |
| Descripción | 128K x 8 SRAM WITH DUAL CHIP ENABLE ULTRA LOW POWER | |
| Fabricantes | Austin Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MT5C1008LL (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
|
No Preview Available !
Austin Semiconductor, Inc.
SRAM
MT5C1008(LL)
Ultra Low Power
128K x 8 SRAM
WITH DUAL CHIP ENABLE
ULTRA LOW POWER
AVAILABLE AS MILITARY
SPECIFICATIONS
•MIL-STD-883, para. 1.2.2 compliant
FEATURES
• High Speed: 30 ns
• Low active power: 715 mW worst case
• Low CMOS standby power: 3.3 mW worst case
• 2.0V data retention, Ultra Low 0.3mW worst
case power dissipation
• Battery backup applications
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1\, CE2, and OE\ options
www.DataSheet4U.com
OPTIONS
• Timing
30ns access
MARKING
-30
• Package(s)
Ceramic DIP (400 mil)
C No. 111
• Temperature
Military (-55°C to +125°C)
MIL
• Options
2V data retention/very low power LL
For more products and information
please visit our web site at
www.austinsemiconductor.com
PIN ASSIGNMENT
(Top View)
32-Pin DIP (C)
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 CE2
29 WE\
28 A13
26 A8
27 A9
25 A11
24 OE\
23 A10
22 CE1\
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
GENERAL DESCRIPTION
The MT5C1008 SRAM is a high-performance CMOS
static RAM organized as 131, 072 words by 8 bits, offering low
active power and ultra low standby and data retention current
levels. Easy memory expansion is provided by an active LOW
Chip Enable (CE1\), an active HIGH Chip Enable (CE2), and
active Low Output Enable (OE\), and three-state drivers.
Writing to the device is accomplished by taking Chip Enable
One (CE1\) and Write Enable (WE\) inputs LOW and Chip
Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A16).
Reading from the device is accomplished by taking
Chip Enable One (CE1\) and Output Enable (OE\) LOW while
forcing Write Enable (WE\) and Chip Enable Two (CE2) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output (I/O0 through I/O7) are placed
in a high-impedance state when the device is deselected (CE1\)
HIGH or CE2 LOW), the outputs are disabled (OE\ HIGH), or
during a write operation (CE1\ LOW, CE2 HIGH, and WE\ LOW).
MT5C1008(LL)
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
1 page  
Austin Semiconductor, Inc.
SRAM
MT5C1008(LL)
Ultra Low Power
SWITCHING CHARACTERISTICS1 (-55oC < TC < 125oC; VCC = 5.0V +10%)
READ CYCLE
Read Cycle Time
PARAMETER
Address to Data Valid
Data Hold from Address Change
CE1\ LOW to Data Valid, CE2 HIGH to Data Valid
OE\ LOW to Data Valid
OE\ LOW to Low Z
OE\ HIGH to High Z
CE1\ LOW to Low Z, CE2 HIGH to Low Z
CE1\ HIGH to High Z, CE2 LOW to High Z
WRITE CYCLE 4
Write Cycle Time
CE1\ LOW to Write End, CE2 HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE\ Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE\ HIGH to Low Z
WE\ LOW to High Z
SYM
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
-30
MIN MAX
30
30
3
30
12
0
8
3
15
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC 30
ns
tSCE
22
ns
tAW 22
ns
tHA 0
ns
tSA 0
ns
tPWE
22
ns
tSD 18
ns
tHD 0
ns
tLZWE
5
ns
tHZWE
8 ns
NOTES
2, 3
3
2, 3
5
3
2, 3
NOTES:
1. Test conditions assume signal transition time of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30pF load capacitance.
2. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5pF as in part (b) of AC Test Loads. Transition is measured ±500mV from steady-state voltage.
3. At any given temperature and voltage condition, tHZCE < tLZCE, tHZOE < tLZOE, and tHZWE < tLZWE for any given device.
4. The internal write time of the memory is defined by the overlap of CE1\ LOW, CE2 HIGH, and WE\ LOW. CE1\ and WE\ must be LOW and CE2 HIGH to initiate a write, and the transition of any of
these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write.
5. The minimum write cycle time for Write Cycle No. 3 (WE\ controlled, OE\ LOW) is the sum of tHZWE and tSD.
MT5C1008(LL)
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet MT5C1008LL.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MT5C1008LL | 128K x 8 SRAM WITH DUAL CHIP ENABLE ULTRA LOW POWER | Austin Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |