|
|
PDF ISL12024 Data sheet ( Hoja de datos )
| Número de pieza | ISL12024 | |
| Descripción | Real-Time Clock/Calendar | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ISL12024 (archivo pdf) en la parte inferior de esta página. Total 25 Páginas | ||
|
No Preview Available !
®
Data Sheet
New Features
October 18, 2006
ISL12024
FN6370.1
Real-Time Clock/Calendar with Embedded
Unique ID
The ISL12024 device is a micro-power real-time clock with
embedded 64-bit unique ID, timing and crystal
compensation, clock/calender, power-fail indicator, two
periodic or polled alarms, intelligent battery backup
switching, and integrated 512 x 8-bit EEPROM configured in
16 Bytes per page.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real-time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
Ordering Information
PART
TEMP
NUMBER
PART
VDD RANGE
PKG.
(Note) MARKING RANGE (°C) PACKAGE DWG. #
ISL12024IBZ 12024IBZ 2.7V to -40 to +85 8 Ld SOIC M8.15
5.5V
(Pb-free)
ISL12024IVZ 2024IVZ
www.DataSheet4U.com
2.7V to -40 to +85 8 Ld TSSOP M8.173
5.5V
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Add “-T” suffix for tape and reel.
Pinouts
X1
X2
IRQ/FOUT
GND
ISL12024
(8 LD SOIC)
TOP VIEW
18
27
36
45
VDD
VBAT
SCL
SDA
VBAT
VDD
X1
X2
ISL12024
(8 LD TSSOP)
TOP VIEW
18
27
36
45
SCL
SDA
GND
IRQ/FOUT
Features
• Real-Time Clock/Calendar
- Tracks Time in Hours, Minutes, and Seconds
- Day of the Week, Day, Month, and Year
- 3 Selectable Frequency Outputs
• 64-bit Unique ID
• Two Non-Volatile Alarms
- Settable on the Second, Minute, Hour, Day of the Week,
Day, or Month
- Repeat Mode (periodic interrupts)
• Automatic Backup to Battery or SuperCap
• On-Chip Oscillator Compensation
- Internal Feedback Resistor and Compensation
Capacitors
- 64 Position Digitally Controlled Trim Capacitor
- 6 Digital Frequency Adjustment Settings to ±30ppm
• 512 x 8 Bits of EEPROM
- 16-Bytes Page Write Mode (32 total pages)
- 8 Modes of BlockLock™ Protection
- Single Byte Write Capability
• High Reliability
- Data Retention: 50 years
- Endurance: 2,000,000 Cycles Per Byte
• I2C Interface
- 400kHz Data Transfer Rate
• 800nA Battery Supply Current
• Package Options
- 8 Ld SOIC and 8 Ld TSSOP Packages
- Pin-compatible with the ISL12026
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Utility Meters
• Audio Video Equipment
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Computer Products
• Security Related Application
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
BlockLock is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL12024
AC Electrical Specifications (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
tDH Output Data Hold Time
From SCL falling edge crossing 30%
of VDD, until SDA enters the 30% to
70% of VDD window.
Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip.
0
10
ns
400 pF
Cpin SDA, and SCL Pin Capacitance
10 pF
tWC Non-volatile Write Cycle Time
12 20 ms
NOTES:
3. IRQ/FOUT Inactive.
4. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz
5. VDD > VBAT +VBATHYS
6. Bit BSW = 0 (Standard Mode), VBAT ≥1.8V
7. Specified at +25°C.
8. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
9. Parameter is not 100% tested.
10. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user (it is the time from valid STOP condition at the end of Write
sequence of a serial interface Write operation) to the end of the self-timed internal non-volatile write cycle.
Timing Diagrams
Bus Timing
tF
tHIGH
tLOW
tR
tHD:STO
SCL
tSU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
tSU:DAT
tHD:STA
tHD:DAT
tAA tDH
tSU:STO
tBUF
Write Cycle Timing
SCL
SDA
8TH BIT OF LAST BYTE
ACK
STOP
CONDITION
tWC
START
CONDITION
5 FN6370.1
October 18, 2006
5 Page 
ISL12024
Alarm Registers (Non-Volatile)
Alarm0 and Alarm1
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
alarm register, multiple registers, or all registers can be
enabled for a match. See “Device Operation” on page 12
and “Application Section” on page 20 for more information.
Control Registers (Non-Volatile)
The Control Bits and Registers described under this section
are non-volatile.
BL Register
BP2, BP1, BP0 - Block Protect Bits
The Block Protect Bits, BP2, BP1 and BP0, determine which
blocks of the array are write protected. A write to a protected
block of memory is ignored. The block protect bits will
prevent write operations to one of eight segments of the
array. The partitions are described in Table 3.
TABLE 3.
PROTECTED ADDRESSES
ISL12024
ARRAY LOCK
000
None (Default)
None
001
010
011
100
101
110
111
180h – 1FFh
100h – 1FFh
000h – 1FFh
000h – 03Fh
000h – 07Fh
000h – 0FFh
000h – 1FFh
Upper 1/4
Upper 1/2
Full Array
First 4 Pages
First 8 Pages
First 16 Pages
Full Array
INT Register: Interrupt Control and
Frequency Output Register
IM, AL1E, AL0E - Interrupt Control and Status Bits
There are two Interrupt Control bits, Alarm 1 Interrupt Enable
(AL1E) and Alarm 0 Interrupt Enable (AL0E) to specifically
enable or disable the alarm interrupt signal output
(IRQ/FOUT). The interrupts are enabled when either the
AL1E or AL0E or both bits are set to ‘1’ and both the FO1
and FO0 bits are set to 0 (FOUT disabled).
The IM bit enables the pulsed interrupt mode. To enter this
mode, the AL0E or AL1E bits are set to “1”, and the IM bit to
“1”. The IRQ/FOUT output will now be pulsed each time an
alarm occurs. This means that once the interrupt mode
alarm is set, it will continue to alarm for each occurring
match of the alarm and present time. This mode is
convenient for hourly or daily hardware interrupts in
microcontroller applications such as security cameras or
utility meter reading.
In this case both Alarms are enabled.
FO1, FO0 - Programmable Frequency Output Bits
These are two output control bits. They select one of three
divisions of the internal oscillator, that is applied to the
IRQ/FOUT output pin. Table 4 shows the selection bits for
this output. When using this function, the Alarm output
function is disabled.
TABLE 4. PROGRAMMABLE FREQUENCY OUTPUT BITS
FO1 FO0
OUTPUT FREQUENCY
00
01
10
11
Alarm output (FOUT disabled)
32.768kHz
4096Hz
1Hz
Oscillator Compensation Registers
There are two trimming options.
- ATR. Analog Trimming Register
- DTR. Digital Trimming Register
These registers are non-volatile. The combination of analog
and digital trimming can give up to -64ppm to +110 ppm of
total adjustment.
ATR Register - ATR5, ATR4, ATR3, ATR2, ATR1,
ATR0: Analog Trimming Register
Six analog trimming bits, ATR0 to ATR5, are provided in
order to adjust the on-chip load capacitance value for
frequency compensation of the RTC. Each bit has a different
weight for capacitance adjustment. For example, using a
Citizen CFS-206 crystal with different ATR bit combinations
provides an estimated ppm adjustment range from -34ppm
to +80ppm to the nominal frequency compensation.
X1
CX1
X2
CX2
CRYSTAL
OSCILLATOR
FIGURE 8. DIAGRAM OF ATR
11 FN6370.1
October 18, 2006
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet ISL12024.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ISL12020 | Low Power RTC | Intersil Corporation |
| ISL12020M | Low Power RTC | Intersil Corporation |
| ISL12021 | Real Time Clock | Intersil Corporation |
| ISL12022 | Low Power RTC |  Intersil |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |