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PDF ISL55110 Data sheet ( Hoja de datos )
| Número de pieza | ISL55110 | |
| Descripción | (ISL55110 / ISL55111) High Speed MOSFET Driver | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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DATASHEET
Dual, High Speed MOSFET Driver
ISL55110, ISL55111
The ISL55110 and ISL55111 are dual high speed MOSFET
drivers intended for applications requiring accurate pulse
generation and buffering. Target applications include
ultrasound, CCD imaging, piezoelectric distance sensing and
clock generation circuits.
With a wide output voltage range and low ON-resistance, these
devices can drive a variety of resistive and capacitive loads
with fast rise and fall times, allowing high-speed operation
with low skew, as required in large CCD array imaging
applications.
The ISL55110, ISL55111 are compatible with 3.3V and 5V
logic families and incorporate tightly controlled input
thresholds to minimize the effect of input rise time on output
pulse width. The ISL55110 has a pair of in-phase drivers while
the ISL55111 has two drivers operating in anti-phase.
ISL55110 and ISL55111 have a power-down mode for low
power consumption during equipment standby times, making
it ideal for portable products.
The ISL55110 and ISL55111 are available in 16 Ld Exposed
pad QFN packaging and 8 Ld TSSOP. Both devices are
specified for operation over the full -40°C to +85°C
temperature range.
Features
• 5V to 12V pulse amplitude
• High current drive 3.5A
• 6ns minimum pulse width
• 1.5ns rise and fall times, 100pF load
• Low skew
• 3.3V and 5V logic compatible
• In-phase (ISL55110) and anti-phase outputs (ISL55111)
• Small QFN and TSSOP packaging
• Low quiescent current
• Pb-free (RoHS compliant)
Applications
• Ultrasound MOSFET driver
• CCD array horizontal driver
• Clock driver circuits
Related Literature
• AN1283, “ISL55110_11EVAL1Z, ISL55110_11EVAL2Z
Evaluation Board User's Manual”
ISL55110 AND ISL55111 DUAL DRIVER
o VDD
VH o
o IN-A
OA o
o
ENABLE-QFN*
o IN-B
**
o PD
OB o
GND o
*ENABLE AVAILABLE IN QFN PACKAGE ONLY
**ISL55111 IN-B IS INVERTING
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
January 29, 2015
FN6228.8
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas LLC 2006-2008, 2011-2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL55110, ISL55111
DC Electrical Specifications VH = +12V, VDD = 2.7V to 5.5V, TA = +25°C, unless otherwise specified. (Continued)
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
(Note 8)
MAX
TYP (Note 8)
SUPPLY CURRENTS
IDD
IDD-PDN
IH
Logic Supply Quiescent Current
Logic Supply Power-down Current
Driver Supply Quiescent Current
PD = Low
PD = High
PD = Low, outputs unloaded
4.0 6.0
12
15
IH_PDN
Driver Supply Power-down Current
PD = High
2.5
UNITS
mA
µA
µA
µA
AC Electrical Specifications VH = +12V, VDD = +3.6V, TA = +25°C, unless otherwise specified.
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
(Note 8)
TYP
SWITCHING CHARACTERISTICS
tR Driver Rise Time
Figure 2, OA, OB:
CL = 100pF/1k
10% to 90%, VOH - VOL = 12V
1.2
tF Driver Fall Time
Figure 2, OA, OB:
CL = 100pF/1k
10% to 90%, VOH - VOL = 12V
1.4
tR Driver Rise Time
Figure 2, OA, OB: CL = 1nF
10% to 90%, VOH - VOL = 12V
6.2
tF Driver Fall Time
Figure 2, OA, OB: CL = 1nF
10% to 90%, VOH - VOL = 12V
6.9
tpdR
Input to Output Propagation Delay
Figure 3, load 100pF/1k
10.9
tpdF Input to Output Propagation Delay
10.7
tpdR
Input to Output Propagation Delay
Figure 3, load 330pF
12.8
tpdF Input to Output Propagation Delay
12.5
tpdR
Input to Output Propagation Delay
Figure 3, load 680pF
14.5
tpdF Input to Output Propagation Delay
14.1
tSkewR
Channel-to-Channel tpdR Spread with Same Figure 3, All loads
Loads Both Channels
<0.5
tSkewF
Channel-to-Channel tpdF Spread with Same Figure 3, All loads
Loads Both Channels
<0.5
FMAX
Maximum Operating Frequency
70
TMIN
Minimum Pulse Width
6
PDEN
Power-down to Power-on Time
650
PDDIS
Power-on to Power-down Time
40
tEN Enable time; ENABLE switched high to low.
40
tDIS Disable time; ENABLE switched low to high.
40
NOTE:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
MAX
(Note 8)
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
Submit Document Feedback
5
FN6228.8
January 29, 2015
5 Page 
ISL55110, ISL55111
Typical Performance Curves (See “Typical Performance Curves Discussion” on page 11) (Continued)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
2.5
VH = 12.0V
680pF
330pF
3.5 4.5
VDD (V)
FIGURE 30. tSkewR vs VDD
5.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
2.5
VH = 12.0V
680pF
330pF
3.5 4.5
VDD (V)
FIGURE 31. tSkewF vs VDD
5.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
3
VDD = 3.3V
680pF
330pF
69
VH (V)
FIGURE 32. tSkewR vs VH
12
Typical Performance Curves
Discussion
rON
The rON source is tested by placing the device in constant drive
high condition and connecting a -50mA constant current
source to the driver output. The voltage drop is measured from
VH to driver output for rON calculations.
The rON sink is tested by placing the device in constant driver
low condition and connecting a +50mA constant current
source. The voltage drop from driver out to ground is measured
for rON calculations.
Dynamic Tests
All dynamic tests are conducted with ISL55110 and ISL55111
evaluation board(s) (ISL55110_11EVAL2Z). Driver loads are
soldered to the evaluation board. Measurements are collected
with P6245 active FET Probes and TDS5104 oscilloscope.
Pulse stimulus is provided by HP8131 pulse generator.
The ISL55110 and ISL55111 evaluation boards provide test
point fields for leadless connection to either an active FET
Submit Document Feedback 11
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
3
VDD = 3.3V
680pF
330pF
69
VH (V)
FIGURE 33. tSkewF vs VH
12
probe or differential probe. “TP - IN_A/_B” test points are used
for monitoring pulse input stimulus. “TP - OA/OB” allows
monitoring of driver output waveforms. C6 and C7 are the
usual placement for driver loads. R3 and R4 are not populated
and are provided for user-specified, more complex load
characterization.
Pin Skew
Pin skew measurements are based on the difference in
propagation delay of the two channels. Measurements are
made on each channel from the 50% point on the stimulus
point to the 50% point on the driver output. The difference in
the propagation delay for Channel A and Channel B is
considered to be skew.
Both rising propagation delay and falling propagation delay are
measured and report as tSkewR and tSkewF.
50MHz Tests
50MHz Tests reported as no load actually include evaluation
board parasitics and a single TEK 6545 FET probe. However, no
driver load components are installed and C6 through C9 and
R3 through R6 are not populated.
FN6228.8
January 29, 2015
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ISL55110.PDF ] | |
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