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PDF ISL22429 Data sheet ( Hoja de datos )
| Número de pieza | ISL22429 | |
| Descripción | Dual Digitally Controlled Potentiometer | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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ISL22429
® Dual Digitally Controlled Potentiometer (XDCP™)
Data Sheet
September 26, 2006
FN6332.1
Low Noise, Low Power, SPI® Bus, 128 Taps,
Wiper Only
The ISL22429 integrates two digitally controlled
potentiometers (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
SPI serial interface. Each potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up the device recalls the contents of the
DCP’s IVR to the corresponding WR.
The DCP can be used as a voltage divider in a wide variety
of applications including control, parameter adjustments, AC
measurement and signal processing.
Pinout
www.DataSheet4U.com
NC
SCK
SDO
GND
RW1
ISL22429
(10 LD MSOP)
TOP VIEW
1 10
29
38
47
56
RW0
SHDN
VCC
SDI
CS
Features
• Two potentiometers in one package
• 128 resistor taps
• SPI serial interface
• Non-volatile storage of wiper position
• Wiper resistance: 70Ω typical @ 3.3V
• Shutdown mode
• Shutdown current 5µA max
• Power supply: 2.7V to 5.5V
• 50kΩ or 10kΩ total resistance
• High reliability
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T < +55°C
• 10 Lead MSOP
• Pb-free plus anneal product (RoHS compliant)
Ordering Information
PART NUMBER
PART MARKING
RESISTANCE OPTION
(kΩ)
TEMP. RANGE
(°C)
PACKAGE
PKG. DWG. #
ISL22429UFU10Z
(Notes 1, 2)
429UZ
50
-40 to +125
10 Ld MSOP
M10.118
(Pb-free)
ISL22429WFU10Z
(Notes 1, 2)
429WZ
10
-40 to +125
10 Ld MSOP
M10.118
(Pb-free)
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add “-TK” suffix for 1,000 Tape and Reel option
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL22429
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (NOTE 5) MAX
UNIT
Hysteresis SHDN, SCK, SDI, and CS Input Buffer
Hysteresis
VOL
Rpu
(Note 14)
SDO Output Buffer LOW Voltage
SDO Pull-up Resistor Off-chip
IOL = 4mA
Maximum is determined by tRO and tFO with
maximum bus load Cbus = 30pF, fSCK =
5MHz
0.05*
VCC
0
V
0.4 V
2 kΩ
Cpin SHDN, SCK, SDI, SDO and CS Pin
(Note 15) Capacitance
10 pF
fSCK
SPI Frequency
5 MHz
tCYC
SPI Clock Cycle Time
200 ns
tWH SPI Clock High Time
100 ns
tWL SPI Clock Low Time
100 ns
tLEAD Lead Time
250 ns
tLAG
Lag Time
250 ns
tSU SDI, SCK and CS Input Setup Time
50 ns
tH SDI, SCK and CS Input Hold Time
50 ns
tRI SDI, SCK and CS Input Rise Time
10 ns
tFI SDI, SCK and CS Input Fall Time
10 20 ns
tDIS SDO Output Disable Time
0 100 ns
tV SDO Output Valid Time
350 ns
tHO SDO Output Hold Time
0 ns
tRO SDO Output Rise Time
Rpu = 2k, Cbus = 30pF
60 ns
tFO SDO Output Fall Time
Rpu = 2k, Cbus = 30pF
60 ns
tCS CS Deselect Time
2 µs
NOTES:
5. Typical values are for TA = +25°C and 3.3V supply voltage.
6. LSB: [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
7. ZS error = V(RW)0/LSB.
8. FS error = [V(RW)127 – VCC]/LSB.
9. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting.
10. INL = [V(RW)i – i • LSB – V(RW)]/LSB for i = 1 to 127
11. VMATCH = [V(RWx)i – V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 3 and y = 0 to 3.
12.
TCV
=
-------M-----a----x----(--V----(---R-----W------)--i--)---–-----M-----i--n----(--V-----(--R-----W------)--i--)------ × ----1---0----6----- for i = 16 to 112 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper
[Max(V(RW)i) + Min(V(RW)i)] ⁄ 2 165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.
13. tWC is the time from the end of a Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle.
14. Rpu is specified for the highest data rate transfer for the device. Higher value pull-up can be used at lower data rates.
15. This parameter is not 100% tested.
5 FN6332.1
September 26, 2006
5 Page 
ISL22429
CS
SCK
SDI
SDO
0 1 0 1 0 0 0 0 0 I3 I2 I1 I0 R3 R2 R1 R0
Don’t Care
0 D6 D5 D4 D3 D2 D1 D0
FIGURE 13. THREE BYTE READ SEQUENCE
Applications Information
Communicating with ISL22429
Communication with ISL22429 proceeds using SPI interface
through the ACR (address 1000b), IVRi (addresses 0000b,
0001b) and WRi (addresses 0000b, 0001b) registers.
The wiper of the potentiometer is controlled by the WRi
register. Writes and reads can be made directly to these
registers to control and monitor the wiper position without
any non-volatile memory changes. This is done by setting
MSB bit at address 1000b to 1.
The non-volatile IVRi stores the power up value of the wiper.
IVRs are accessible when MSB bit at address 1000b is set
to 0. Writing a new value to the IVRi register will set a new
power up position for the wiper. Also, writing to this register
will load the same value into the corresponding WRi as the
IVRi. Reading from the IVRi will not change the WRi, if its
contents are different.
Examples:
B. Reading from the WR:
This sequence will read the value from the WR1 (volatile):
Write to ACR first to access the volatile WRs
Send the ID byte, Instruction Byte, then the Data byte
010100001100100011000000
(Sent to SDI)
Read the data from WR1 (Addr 0001b)
Send the ID byte, Instruction Byte, then Read the Data byte
0101000010110001xxxxxxxx
(Out on SDO)
A. Writing to the IVR:
This sequence will write a new value (77h) to the IVR0(non-volatile):
Set the ACR (Addr 1000b) for NV write (40h)
Send the ID byte, Instruction Byte, then the Data byte
010100001100100001000000
(Sent to SDI)
Set the IVR0 (Addr 0000b) to 77h
Send the ID byte, Instruction Byte, then the Data byte
010100001100000001110111
(Sent to SDI)
11 FN6332.1
September 26, 2006
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ISL22429.PDF ] | |
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