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ISL22326 の電気的特性と機能

ISL22326のメーカーはIntersil Corporationです、この部品の機能は「Dual Digitally Controlled Potentiometers」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL22326
部品説明 Dual Digitally Controlled Potentiometers
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL22326 Datasheet, ISL22326 PDF,ピン配置, 機能
Data Sheet
ISL22326
Dual Digitally Controlled Potentiometers (XDCP™)
September 9, 2015
FN6176.3
Low Noise, Low Power, I2CBus, 128 Taps
The ISL22326 integrates two digitally controlled potentiometers
(XDCP) and non-volatile memory on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. Each potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up the device recalls the contents of the two
DCP’s IVR to the corresponding WRs.
The DCPs can be used as three-terminal potentiometers or
as two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Pinouts
VCC
SHDN
RH0
RL0
RW0
A2
SCL
ISL22326
(14 LD TSSOP)
TOP VIEW
1 14
2 13
3 12
4 11
5 10
69
78
A1
A0
RH1
RL1
RW1
GND
SDA
Features
• Two potentiometers in one package
• 128 resistor taps
• I2C serial interface
- Three address pins, up to eight devices/bus
• Non-volatile storage of wiper position
• Wiper resistance: 70typical @ VCC = 3.3V
• Shutdown mode
• Shutdown current 5µA max
• Power supply: 2.7V to 5.5V
• 50kor 10ktotal resistance
• High reliability
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T < +55°C
• 14 Ld TSSOP or 16 Ld QFN package
• Pb-free (RoHS compliant)
ISL22326
(16 LD QFN)
TOP VIEW
16 15 14 13
RH0 1
12 RH1
RL0 2
RW0 3
11 RL1
10 RW1
NC 4
9 NC
5678
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas LLC.
Copyright Intersil Americas LLC. 2006, 2008, 2009, 2015. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL22326 pdf, ピン配列
ISL22326
Pin Descriptions
TSSOP PIN
NUMBER
QFN PIN
NUMBER
PIN NAME
DESCRIPTION
1
15
VCC
Power supply pin
2
16
SHDN
Shutdown active low input
3
1
RH0
“High” terminal of DCP0
4 2 RL0 “Low” terminal of DCP0
5
3
RW0
“Wiper” terminal of DCP0
6 5 A2 Device address input for the I2C interface
7 6 SCL Open drain I2C interface clock input
8
7
SDA
Open drain Serial data I/O for the I2C interface
9
8
GND
Device ground pin
10
10
RW1
“Wiper” terminal of DCP1
11 11 RL1 “Low” terminal of DCP1
12
12
RH1
“High” terminal of DCP1
13 13 A0 Device address input for the I2C interface
14 14 A1 Device address input for the I2C interface
4, 9 NC No connection
EPAD*
Exposed Die Pad internally connected to GND
*Note: PCB thermal land for QFN EPAD should be connected to GND plane or left floating. For more information refer to
http://www.intersil.com/data/tb/TB389.pdf
3 FN6176.3
September 9, 2015


3Pages


ISL22326 電子部品, 半導体
ISL22326
Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN TYP MAX
(Note 20) (Note 4) (Note 20)
tD Power-up Delay
VRCegCisatbeor vreecValpl ocro,mtopDleCtePd,InaintidalI2VCaluIneterface
in standby state
3
EEPROM SPECIFICATION
EEPROM Endurance
1,000,000
EEPROM Retention
Temperature T < +55°C
50
tWC Non-volatile Write Cycle Time
(Note 18)
12 20
SERIAL INTERFACE SPECIFICATIONS
VIL A2, A1, A0, SHDN, SDA, and SCL
Input Buffer LOW Voltage
-0.3 0.3*VCC
VIH A2, A1, A0, SHDN, SDA, and SCL
Input Buffer HIGH Voltage
0.7*VCC
VCC + 0.3
Hysteresis SDA and SCL Input Buffer Hysteresis
VOL SDA Output Buffer LOW Voltage,
Sinking 4mA
0.05*VCC
0
0.4
Cpin
A2, A1, A0, SHDN, SDA, and SCL Pin
(Note 19) Capacitance
10
fSCL
tsp
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed
400
50
tAA
tBUF
SCL falling edge to SDA output data
valid
Time the Bus Must be Free Before the
Start of a New Transmission
SCL falling edge crossing 30% of VCC, until
SDA exits the 30% to 70% of VCC window
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VCC
during the following START condition
1300
900
tLOW
tHIGH
tSU:STA
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
tHD:STA START Condition Hold Time
tSU:DAT Input Data Setup Time
tHD:DAT Input Data Hold Time
Measured at the 30% of VCC crossing
Measured at the 70% of VCC crossing
SCL rising edge to SDA falling edge; both
crossing 70% of VCC
From SDA falling edge crossing 30% of VCC
to SCL falling edge crossing 70% of VCC
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
From SCL rising edge crossing 70% of VCC
to SDA entering the 30% to 70% of VCC
window
1300
600
600
600
100
0
tSU:STO
tHD:STO
tDH
STOP Condition Setup Time
STOP Condition Hold Time for Read,
or Volatile Only Write
Output Data Hold Time
From SCL rising edge crossing 70% of VCC
to SDA rising edge crossing 30% of VCC
From SDA rising edge to SCL falling edge;
both crossing 70% of VCC
From SCL falling edge crossing 30% of VCC,
until SDA enters the 30% to 70% of VCC
window
600
1300
0
tR SDA and SCL Rise Time
From 30% to 70% of VCC
20 +
0.1*Cb
250
tF SDA and SCL Fall Time
From 70% to 30% of VCC
20 +
0.1*Cb
250
UNIT
ms
Cycles
Years
ms
V
V
V
V
pF
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6 FN6176.3
September 9, 2015

6 Page



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共有リンク

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