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VP5511C の電気的特性と機能

VP5511CのメーカーはZarlink Semiconductorです、この部品の機能は「(VP5311C / VP5511C) NTSC/PAL Digital Video Encoder」です。


製品の詳細 ( Datasheet PDF )

部品番号 VP5511C
部品説明 (VP5311C / VP5511C) NTSC/PAL Digital Video Encoder
メーカ Zarlink Semiconductor
ロゴ Zarlink Semiconductor ロゴ 




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VP5511C Datasheet, VP5511C PDF,ピン配置, 機能
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1 Page





VP5511C pdf, ピン配列
VP5311C/VP5511C
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated): As specified in Recommended Operating Conditions
DC CHARACTERISTICS
Parameter
Conditions
Symbol Min. Typ. Max. Units
Digital Inputs TTL compatible (except SDA, SCL)
Input high voltage
Input low voltage
Digital Inputs SDA, SCL
Input high voltage
Input low voltage
Input high current
VIN = VDD
Input low current
VIN = VSS
Digital Outputs CMOS compatible
Output high voltage
IOH = -1mA
Output low voltage
IOL = +4mA
Digital Output SDA
Output low voltage
IOL = +6mA
VIH 2.0
VIL
VIH 0.7 VDD
VIL
IIH
IIL
VOH
VOL
3.7
VOL
V
0.8 V
0.3 VDD
10
-10
V
V
µA
µA
V
0.4 V
0.6 V
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated): As specified in Recommended Operating Conditions
DC CHARACTERISTICS DACs
Parameter
Symbol Min. Typ. Max.
Accuracy (each DAC)
Integral linearity error
Diffential linearity error
DAC matching error
Monotonicity
LSB size
Internal reference voltage
Internal reference voltage output impedance
Reference Current (VREF/RREF) RREF = 769
DAC Gain Factor (VOUT = KDAC x IREF x RL), VOUT = DAC code 511
Peak Glitch Energy (see fig.3)
INL
DNL
VREF
ZR
IREF
KDAC
guaranteed
66.83
1.050
27k
1.3699
24.93
50
±1.5
±1
±5
Units
LSB
LSB
%
µA
V
mA
pV-s
CVBS, Y and C - NTSC (pedestal enabled)
Maximum output, relative to sync bottom
White level relative to black level
Black level relative to blank level
Blank level relative to sync level
Colour burst peak - peak
DC offset (bottom sync)
33.75
17.64
1.40
7.62
7.62
0.40
mA
mA
mA
mA
mA
mA
CVBS, Y and C - PAL
Maximum output
White level relative to black level
White level relative to sync level
Black level relative to sync level
Colour burst peak - peak
DC offset (bottom sync)
34.15
18.71
26.73
8.02
8.02
0.00
mA
mA
mA
mA
mA
mA
Note: All figures are for: RREF = 769RL = 37.5. When the device is set up in NTSC mode there is a +0.25% error in the PAL
levels. If RL = 75then RREF = 1538.
ABSOLUTE MAXIMUM RATINGS
Supply voltage
VDD, AVDD
Voltage on any non power pin
Ambient operating temperature
Storage temperature
-0·3 to 7·0V
-0·3 to VDD+0·3V
0 to 70°C
-55°C to 150°C
Note: Stresses exceeding these listed under Absolute
Maximum Ratings may induce failure. Exposure to Absolute
Maximum Ratings for extended periods may reduce
reliability. Functionality at or above these conditions is not
implied.
2


3Pages


VP5511C 電子部品, 半導体
VP5311C/VP5511C
PIN DESCRIPTIONS
Pin Name
Pin No. Description
PD7-0
D0-7
PXCK
CLAMP
COMPSYNC
30 - 37
1-8
12
14
15
8 Bit Pixel Data inputs clocked by PXCK. PD0 is the least significant bit, corresponding to Pin
37. These pins are internally pulled low.
8 Bit General Purpose Port input/output. D0 is the least significant bit, corresponding to Pin 1.
These pins are internally pulled low.
27MHz Pixel Clock input. The VP5311C/5511C internally divides PXCK by two to provide the
pixel clock.
The CLAMP output signal is synchronised to COMPSYNC output and indicates the position of
the BURST pulse, (lines 10-263 and 273-525 for NTSC and PAL-M; lines 6-310 and 319-623
for PAL-B,D, G,I,N(Argentina)).
Composite sync pulse output. This is an active low output signal.
TDO
TDI
TMS
TCK
SA1
SA2
SCL
SDA
RESET
REFSQ
VREF
DAC GAIN
COMP
LUMAOUT
COMPOUT
CHROMAOUT
VDD
AVDD
GND
AGND
16
17
18
19
21
22
23
25
27
28
41
42
43
45
47
49
10, 13, 24,
26, 39
44, 50,
51, 52
9, 11, 20,
29, 38
40, 46, 48
JTAG Data output port.
JTAG Data input port.
JTAG mode select input.
JTAG clock input.
I2C slave address select
I2C slave address select.
Standard I2C bus serial clock input.
Standard I2C bus serial data input/output.
Master reset. This is an asynchronous, active low, input signal and must be asserted for a
minimum 200ns in order to reset the VP5311C/5511C.
Reference square wave input used only during Genlock mode.
Voltage reference input/output. This pin is nominally 1.055V and should be decoupled with a
100nF capacitor to GND.
DAC full scale current control. A resistor connected between this pin and GND sets the
magnitude of the video output current. An internal loop amplifier controls a reference current
flowing through this resistor so that the voltage across it is equal to the Vref voltage.
DAC compensation. A 100nF ceramic capacitor must be connected between pin 43 and pin
44.
True luminance, composite and chrominance video signal outputs. These are high
impedance current source outputs. A DC path to GND must exist from each of these pins.
Positive supply input. All VDD pins must be connected.
Analog positive supply input. All AVDD pins must be connected.
Negative supply input. All GND pins must be connected.
Negative supply input. All AGND pins must be connected.
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共有リンク

Link :


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