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PDF VP16256 Data sheet ( Hoja de datos )
| Número de pieza | VP16256 | |
| Descripción | Programmable FIR FIlter | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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VP16256
Programmable FIR FIlter
Advance Information
DS4548
ISSUE 4.0
August 1998
The VP16256 contains sixteen multiplier - accumulators, which
can be multi cycled to provide from 16 to 128 stages of digital filtering.
Input data and coefficients are both represented by 16-bit two’s
PIN 1
complement numbers with coefficients converted internally to 12 bits
and the results being accumulated up to 32 bits.
In 16-tap mode the device samples data at the system clock rate
of up to 40MHz. If a lower sample rate is acceptable then the number
of stages can be increased in powers of two up to a maximum of 128.
Each time the number of stages is doubled, the sample clock rate
must be halved with respect to the system clock. With 128 stages the
PIN 1 IDENT
PIN
208
sample clock is therefore one eighth of the system clock.
In all speed modes devices can be cascaded to provide filters of
any length, only limited by the possibility of accumulator overflow. The
32-bit results are passed between cascaded devices without any
intermediate scaling and subsequent loss of precision.
The device can be configured as either one long filter or two
separate filters with half the number of taps in each. Both networks
can have independent inputs and outputs.
Both single and cascaded devices can be operated in decimate-
by-two mode. The output rate is then half the input rate, but twice the
number of stages are possible at a given sample rate. A single device
with a 40MHz clock would then, for example, provide a 128-stage low
pass filter, with a 10MHz input rate and 5MHz output rate.
Coefficients are stored internally and can be down loaded from
GH208
a host system or an EPROM. The latter requires no additional
support, and is used in stand alone applications. A full set of
Pin identification diagram (top view)
coefficients is then automatically loaded at power on, or at the request
See Table 1 for pin descriptions and Table 2 for pinout
of the system. A single EPROM can be used to provide coefficiwewnwt.DsataSheet4U.com
for up to 16 devices.
FEATURES
EPROM
ADDR DATA
CHANGE
COEFF
POWER-ON
RESET
I Sixteen MACs in a Single Device
I Basic Mode is 16-Tap Filter at up to 40MHz
Sample Rates
I Programmable to give up to 128 Taps with
INPUT
DATA
RES
VP
16256
OUTPUT
DATA
EPROM
SCLK
GND
Sampling Rates Proportionally Reducing to 5MHz
I 16-bit Data and 32-bit Accumulators
I Can be configured as One Long Filter or Two Half-
Length Filters
I Decimate-by-two Option will Double the Filter
Length
I Coefficients supplied from a Host System or a local
Fig. 1 A dual filter application
EPROM
I 208-Pin Plastic PowerQuad PQ2 Package
ANALOG
INPUT
EPROM
ADDR DATA
CHANGE
COEFF
POWER-ON
RESET
ADC
RES
COEFFICIENTS
VP
16256
EPROM
OUTPUT
DATA
CLKOP
SCLK GND
Fig. 2 Typical system application
APPLICATIONS
I High Performance Commercial Digital Filters
I Matrix Multiplication
I Correlation
I High Performance Adaptive Filtering
ORDERING INFORMATION
VP16256-27/CG/GH1N 27MHz, Commercial
PowerQuad PQ2 package (GH208)
VP16256-40/CG/GH1N 40MHz, Commercial
PowerQuad PQ2 package (GH208)
plastic
plastic
1 page  
VP16256
DATA
OUT
ACCUMULATE
EXPANSION
IN
DATA
DELAY LINE
DATA
DELAY LINE
DATA
DELAY LINE
DATA
DELAY LINE
DATA
IN
COEFF
RAM
ADDER
Z21
COEFF
RAM
ADDER
Z21
COEFF
RAM
ADDER
Z21
COEFF
RAM
ADDER
RESULT
OUT
Z21
Fig. 4 Filter network diagram
SINGLE FILTER OPTIONS
When operating as a single filter the device accepts data on
the 16-bit DA bus at the selected sample rate, see Figs. 5 and 6.
Results are presented on the 32-bit F bus, which may be
tristated using the OEN input. Signal OEN is registered onto the
device and does not therefore take effect until the first SCLK
rising edge. Devices may be cascaded this allows filters with
more taps than available from a single device. To accomplish
this two further buses are utilised. The DB bus presents the
input data to the next device in cascade after the appropriate
delay, while, partial results are accepted on the
X bus.
Single filter mode is selected by setting control register bit
15 to a one. The required filter length is then selected using
control register bits 14 and 13 as summarised in Table 3. The
options define the number of times each multiplier accumulator
is used per sample clock period. This can be once, twice, four
times, or eight times.
In addition a normal/decimate bit (CR12) allows the filter
length to be doubled at any sample rate. This is possible when
the filter coefficients are selected to produce a low pass filter,
since the filtered output would then not contain the higher
frequency components present in the input. The Nyquist
criterion, specifying that the sampling rate must be at least
double the highest frequency component, can still then be
satisfied even though the sampling rate has been halved.
CR Input
14 13 12 Rate
Output Filter Setup
Rate Length Latency
0 0 0 SCLK
0 0 1 SCLK
0 1 0 SCLK/2
0 1 1 SCLK/2
1 0 0 SCLK/4
1 0 1 SCLK/4
1 1 0 SCLK/8
SCLK
SCLK/2
SCLK/2
SCLK/4
SCLK/4
SCLK/8
SCLK/8
16 Taps
32 Taps
32 Taps
64 Taps
64 Taps
128 Taps
128 Taps
Table 3 Single Filter options
16
17
16
18
20
24
24
The system clock latency for a single device is shown in
Table 3. This is defined as the delay from a particular data
sample being available on the input pins to the first result
including that input appearing on the output pins. It does not
include the delay needed to gather N samples, for an N tap filter,
before a mathematically correct result is obtained.
DA15:0
F31:0 OEN
NETWORK
A
MUX
DUAL
MODE
NETWORK
B
SINGLE
MODE
DB15:0
X31:0
Fig. 5 Single Filter bus utilisation
5
5 Page 
VP16256
swap on every data sampling clock. This function does not
depend on the status of SWAP or bit, and the lower bank will be
initially selected after FEN goes active. The option can be used
to implement filters with complex coefficients.
LOADING COEFFICIENTS
When the device is to operate in a stand alone application
then the coefficients can be down loaded as a complete set from
a previously programmed EPROM. Alternatively if the system
contains a microprocessor they can be individually transferred
from a remote master under software control. In any mode the
system clock must be present and stable during the transfer, and
the addressing scheme is such that the least significant address
specifies the coefficient applied to the first multiplier seen by
incoming data.
The addresses used during the load operation are those
illustrated in Fig. 13. The Control Register is loaded when CCS
is high. In byte mode address A0 is used to select the portion of
control register loaded, otherwise the address bits are redundant.
When an EPROM is used to provide coefficients, this redundancy
causes the number of locations needed for any device to be
double that for the coefficients alone.
AUTO EPROM LOAD
When EPROM is tied low, the VP16256 assumes the role of
a master device in the system and controls the loading of
coefficients from an external EPROM, see Fig.15. A load
sequence commences when the RES input goes high, and will
continue until every coefficient has been loaded. BUSY goes high
to indicate that a load sequence is occurring and the filter output
is invalid. The device will not commence a filter operation until the
FEN edge is received after BUSY has gone low. This requirement
can be avoided if FRUN is tied high.
The address bus pins become outputs on the Master device,
and produce a new address every four system clock periods. This
four clock interval, minus output delays and the data set up time,
defines the available EPROM access time.
The coefficients are always loaded as bytes. The state of the
BYTE pin on the master device is ignored. This arrangement also
allows the eight most significant coefficient bus pins (C15:8) to be
used for other purposes as described later. Since the 16-bit
coefficients are loaded in two bytes the A0 pin specifies the
required byte. The maximum number of stored coefficients is
128, eight address outputs are therefore provided for the
EPROM. These eight outputs from the Master must also drive the
address inputs on the slave devices.
SCLK
A7:0
CCS
RES
BUSY
00 01 00 01
LOAD MASTER CONTROL LOAD FIRST COEFFICIENT
REGISTER
VALID ADDR VALID ADDR
LOAD LAST COEFFICIENT
Fig. 14a EPROM load sequence
00
SCLK
A7:0
CCS
C15:12
FE FF
0000
LOAD LAST
MASTER
COEFFICIENT
00 01 00 01
FE FF 00 01 00 01
0001
0001
0010
LOAD SLAVE 1
CONTROL
REGISTER
LOAD SLAVE 1
COEFFICIENTS
LOAD LAST
SLAVE 1
COEFFICIENT
Fig. 14b EPROM load sequence for a cascaded system
LOAD SLAVE 2
CONTROL
REGISTER
LOAD SLAVE 2
COEFFICIENTS
Fig. 14 EPROM load sequence timing diagrams
11
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| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet VP16256.PDF ] | |
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