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PDF MC74LCX543 Data sheet ( Hoja de datos )

Número de pieza MC74LCX543
Descripción LOW-VOLTAGE CMOS OCTAL LATCHING TRANSCEIVER
Fabricantes Motorola Semiconductors 
Logotipo Motorola Semiconductors Logotipo



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No Preview Available ! MC74LCX543 Hoja de datos, Descripción, Manual

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
Low-Voltage CMOS Octal
Latching Transceiver
With 5V-Tolerant Inputs and Outputs
(3-State, Non-Inverting)
The MC74LCX543 is a high performance, non–inverting octal latching
transceiver operating from a 2.7 to 3.6V supply. High impedance TTL
compatible inputs significantly reduce current loading to input drivers
while TTL compatible outputs offer improved switching noise
performance. A VI specification of 5.5V allows MC74LCX543 inputs to be
safely driven from 5V devices. The MC74LCX543 is suitable for memory
address driving and all TTL level bus oriented transceiver applications.
For data flow from A to B with the EAB LOW, the A–to–B Output
Enable (OEAB) must be LOW in order to enable data to the B bus, as
indicated in the Function Table. With EAB LOW, a LOW signal on the
A–to–B Latch Enable (LEAB) input makes the A–to–B latches
transparent; a subsequent LOW–to–HIGH transition of the LEAB signal
will latch the A latches, and the outputs no longer change with the A
inputs. With EAB and OEAB both LOW, the 3–State B output buffers are
active and reflect the data present at the output of the A latches. Control
of data flow from B to A is symetric to that above, but uses the EBA,
LEBA, and OEBA inputs.
MC74LCX543
LOW–VOLTAGE CMOS
OCTAL LATCHING
TRANSCEIVER
24
1
DW SUFFIX
PLASTIC SOIC
CASE 751E–04
Designed for 2.7 to 3.6V VCC Operation
5V Tolerant — Interface Capability With 5V TTL Logic www.DataSheet4U.com
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0V
LVTTL Compatible
LVCMOS Compatible
24mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (10µA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds 500mA
ESD Performance: Human Body Model >2000V; Machine Model >200V
Pinout: 24–Lead Package (Top View)
VCC EBA B0 B1 B2 B3 B4 B5 B6 B7 LEAB OEAB
24 23 22 21 20 19 18 17 16 15 14 13
24
1
24
1
SD SUFFIX
PLASTIC SSOP
CASE 940D–03
DT SUFFIX
PLASTIC TSSOP
CASE 948H–01
PIN NAMES
Pins
Function
OExx
Exx
LExx
A0–A7
B0–B7
Output Enable Inputs
Enable Inputs
Latch Enable Inputs
3–State Inputs/Outputs
3–State Inputs/Outputs
1 2 3 4 5 6 7 8 9 10 11 12
LEBA OEBA A0 A1 A2 A3 A4 A5 A6 A7 EAB GND
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
11/96
© Motorola, Inc. 1996
1
REV 0.3

1 page




MC74LCX543 pdf
CAPACITIVE CHARACTERISTICS
Symbol
CIN
CI/O
CPD
Parameter
Input Capacitance
Input/Output Capacitance
Power Dissipation Capacitance
MC74LCX543
Condition
VCC = 3.3V, VI = 0V or VCC
VCC = 3.3V, VI = 0V or VCC
10MHz, VCC = 3.3V, VI = 0V or VCC
Typical
7
8
25
Unit
pF
pF
pF
An
or Bn
Bn
or An
1.5V
tPLH, tPHL
1.5V
2.7V
0V
VOH
VOL
WAVEFORM 1 – A/B to B/A PROPAGATION DELAYS
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns
OExx
or Exx
1.5V
An
or Bn
tPZH
An
or Bn
tPZL
1.5V
tPHZ
1.5V
tPLZ
1.5V
2.7V
0V
VOH – 0.3V
0V
3.0V
VOL + 0.3V
WAVEFORM 2 – OExx/Exx to A or B OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns
Figure 1. AC Waveforms
LCX DATA
BR1339 — REV 3
5
MOTOROLA

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