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PDF ISL90840 Data sheet ( Hoja de datos )
| Número de pieza | ISL90840 | |
| Descripción | Low Noise/Low Power/I2C Bus/256 Taps | |
| Fabricantes | Intersil Corporation | |
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ISL90840
Quad Digitally Controlled Potentiometers (XDCP™)
Data Sheet
July 27, 2005
FN8086.0
Low Noise, Low Power I2C® Bus, 256 Taps
The ISL90840 integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS integrated
circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. Each potentiometer has an associated
Wiper Register (WR) that can be directly written to and read
by the user. The contents of the WR controls the position of
the wiper.
The DCPs can be used as three-terminal potentiometers or
as two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Ordering Information
PART NUMBER
PACKAGE
TEMP
RANGE
(°C)
RESISTANCE
OPTION
(Ω)
ISL90840UIV2027 20 Ld TSSOP -40 to +85
50K
ISL90840UIV2027Z 20 Ld TSSOP -40 to +85
(Notes 1 & 2)
(Pb-Free)
50K
ISL90840WIV2027 20 Ld TSSOP -40 to +85
10K
ISL90840WIV2027Z 20 Ld TSSOP -40 to +85
(Notes 1 & 2)
(Pb-Free)
10K
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-
free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
2. Contact factory for availability.
Features
• Four potentiometers in one package
• 256 resistor taps - 0.4% resolution
• I2C serial interface
- Three address pins, up to eight devices/bus
• Wiper resistance: 70Ω typical @ 3.3V
• Standby current <5µA max
• Power supply: 2.7V to 5.5V
• 50kΩ, 10kΩ total resistance
• 20 Lead TSSOP
• Pb-free plus anneal available (RoHS compliant)
Pinout
ISL90840
(20 LEAD TSSOP)
TOP VIEW
RH3
RL3
RW3
A2
SCL
SDA
GND
RW2
RL2
RH2
1
2
3
4
5
6
7
8
9
10
20 RW0
19 RL0
18 RH0
17 D.N.C.
16 VCC
15 A1
14 A0
13 RH1
12 RL1
11 RW1
Functional Diagram
VCC
RH0
RH1
RH2
RH3
SCL
SDA
A0
A1
A2
I2C
INTERFACE
GND
RL0 RW0 RL1 RW1 RL2
RW2 RL3
RW3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL90840
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (NOTE 1)
tF SDA and SCL fall time
(Note 15)
From 70% to 30% of VCC
20 +
0.1 * Cb
Cb Capacitive loading of SDA or SCL
(Note 15)
Total on-chip and off-chip
10
Rpu
(Note 15)
SDA and SCL bus pull-up resistor off- Maximum is determined by tR and tF
chip For Cb = 400pF, max is about 2~2.5kΩ.
For Cb = 40pF, max is about 15~20kΩ
1
tSU:A
tHD:A
A2, A1 and A0 setup time
A2, A1 and A0 hold time
Before START condition
After STOP condition
600
600
SDA vs SCL Timing
MAX
250
400
tF
tHIGH
tLOW
tR
UNIT
ns
pF
kΩ
ns
ns
SCL
tSU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
tSU:DAT
tHD:STA
tHD:DAT
tAA tDH
tSU:STO
tBUF
A0, A1, and A2 Pin Timing
SCL
START
SDA IN
A0, A1, OR A2
tSU:A
CLK 1
STOP
tHD:A
5 FN8086.0
July 27, 2005
5 Page 
ISL90840
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL90840 responds with an ACK. At this time, the device
enters its standby state (See Figure 17).
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 18). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the ISL90840 responds with an ACK. Then the ISL90840
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each
byte. The master terminates the read operation (issuing a
STOP condition) following the last bit of the last Data Byte
(See Figure 18).
The Data Bytes are from the registers indicated by an
internal pointer. This pointer initial value is determined by the
Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 03h, the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
11 FN8086.0
July 27, 2005
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ISL90840.PDF ] | |
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