|
|
74LVC132AのメーカーはNXP Semiconductorsです、この部品の機能は「Quad 2-Input NAND Schmitt Trigger」です。 |
部品番号 | 74LVC132A |
| |
部品説明 | Quad 2-Input NAND Schmitt Trigger | ||
メーカ | NXP Semiconductors | ||
ロゴ | |||
このページの下部にプレビューと74LVC132Aダウンロード(pdfファイル)リンクがあります。 Total 15 pages
www.DataSheet4U.com
74LVC132A
Quad 2-input NAND Schmitt trigger
Rev. 01 — 15 December 2006
Product data sheet
1. General description
The 74LVC132A is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
The 74LVC132A provides four 2-input NAND gates with Schmitt trigger inputs. It is
capable of transforming slowly changing input signals into sharply defined, jitter-free
output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage VT+ and the negative voltage VT− is defined as the input
hysteresis voltage VH.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V environment.
2. Features
s Wide supply voltage range from 2.3 V to 3.6 V
s 5 V tolerant inputs for interfacing with 5 V logic
s CMOS low power consumption
s Direct interface with TTL levels
s Unlimited rise and fall times
s Inputs accept voltages up to 5.5 V
s Complies with JEDEC standard JESD8-B/JESD36
s ESD protection:
x HBM JESD22-A114-D exceeds 2000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101-C exceeds 1000 V
s Specified from −40 °C to +85 °C and −40 °C to +125 °C
3. Applications
s Wave and pulse shaper
s Astable multivibrator
s Monostable multivibrator.
1 Page www.DataSheet4U.com
NXP Semiconductors
6. Pinning information
6.1 Pinning
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
74LVC132A
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
001aaf590
Fig 4. Pin configuration SO14 and TSSOP14
6.2 Pin description
Table 2.
Symbol
1A
1B
1Y
2A
2B
2Y
GND
3Y
3A
3B
4Y
4A
4B
VCC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
data input
data input
data output
data input
data input
data output
ground (0 V)
data output
data input
data input
data output
data input
data input
supply voltage
74LVC132A
Quad 2-input NAND Schmitt trigger
74LVC132A
terminal 1
index area
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND(1)
13 4B
12 4A
11 4Y
10 3B
9 3A
001aaf591
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 5. Pin configuration DHVQFN14
74LVC132A_1
Product data sheet
Rev. 01 — 15 December 2006
© NXP B.V. 2006. All rights reserved.
3 of 15
3Pages www.DataSheet4U.com
NXP Semiconductors
74LVC132A
Quad 2-input NAND Schmitt trigger
11. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.
Symbol Parameter
Conditions
−40 °C to +85 °C
Min Typ[1] Max
tpd
propagation delay
nA, nB to nY; see Figure 6 [2]
VCC = 1.2 V
- 18.0 -
VCC = 1.65 V to 1.95 V
2.0 7.2 12.8
VCC = 2.3 V to 2.7 V
1.5 4.0 7.6
VCC = 2.7 V
1.5 3.8 7.6
tsk(o)
CPD
output skew time
power dissipation
capacitance
VCC = 3.0 V to 3.6 V
per buffer; VI = GND to VCC
VCC = 1.65 V to 1.95 V
1.5
[3] -
[4]
-
3.4
-
10.5
6.4
1.0
-
VCC = 2.3 V to 2.7 V
- 10.8 -
VCC = 3.0 V to 3.6 V
- 11.4 -
−40 °C to +125 °C Unit
Min Max
- - ns
2.0 16.0 ns
1.5 9.6 ns
1.5 9.6 ns
1.5 8.0 ns
- 1.5 ns
- - pF
- - pF
- - pF
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
12. Waveforms
nA, nB input
VM
tPHL
tPLH
nY output
VM
VM = 1.5 V at VCC ≥ 2.7 V.
VM = 0.5 × VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 6. The input (nA, nB) to output (nY) propagation delays
mna213
74LVC132A_1
Product data sheet
Rev. 01 — 15 December 2006
© NXP B.V. 2006. All rights reserved.
6 of 15
6 Page | |||
ページ | 合計 : 15 ページ | ||
|
PDF ダウンロード | [ 74LVC132A データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
74LVC132A | Quad 2-Input NAND Schmitt Trigger | NXP Semiconductors |