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VSC8111 の電気的特性と機能

VSC8111のメーカーはVitesse Semiconductorです、この部品の機能は「ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux」です。


製品の詳細 ( Datasheet PDF )

部品番号 VSC8111
部品説明 ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux
メーカ Vitesse Semiconductor
ロゴ Vitesse Semiconductor ロゴ 




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VSC8111 Datasheet, VSC8111 PDF,ピン配置, 機能
Data Sheet
VSC8111
www.DataSheet4U.com
VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 155/622 Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
Features
• Operates at Either STS-3/STM-1 (155.52 Mb/s) or
STS-12/STM-4 (622.08 Mb/s) Data Rates
• Compatible with Industry ATM UNI Devices
• On Chip Clock Generation of the 155.52 Mhz
or 622.08 Mhz High Speed Clock
• Dual 8 Bit Parallel TTL Interface
• Loss of Signal (LOS) Control
• Provides Equipment, Facilities and Split Loop-
back Modes as well as Loop Timing Mode
• Meets Bellcore, ITU and ANSI Specifications for
Jitter Performance
• Single 3.3V Supply Voltage
• Low Power - 1.4 Watts Maximum
• SONET/SDH Frame Detection and Recovery
• 100 PQFP Package
General Description
The VSC8111 is an ATM/SONET/SDH compatible transceiver integrating an on-chip clock multiplication
unit (PLL) for the high speed clock and 8 bit serial-to-parallel and parallel-to-serial data conversion. The high
speed clock generated by the on-chip PLL is selectable for 155.52 or 622.08 MHz operation. The demultiplexer
contains SONET/SDH frame detection and recovery. In addition, the device provides both facility and equip-
ment loopback modes and two loop timing modes. The part is packaged in a 100 PQFP with an integrated heat
spreader for optimum thermal performance and reduced cost. The VSC8111 provides an integrated solution for
ATM physical layers and SONET/SDH systems applications.
VSC8111 Block Diagram
EQULOOP
LOSTTL
LOSPOL
LOS (Internal Signal)
RXDATAIN+/-
DQ
RXCLKIN+/-
0
1
FRAMER
OOF
FP
0 1:8
8
DEMUX
DQ
RXOUT[7:0]
1
0
Divide-by-8
1
RXLSCKOUT
TXDATAOUT+/-
TXCLKOUT+/-
FACLOOP
QD
1
0
1
0
10
8:1
MUX
8
QD
Divide-by-8
TXIN[7:0]
TXLSCKIN
TXLSCKOUT
Divide-by-3/12
RX50MCK
LOOPTIM0
CMU
1
0
REFCLK
LOOPTIM1
LOS
EQULOOP
G52142-0, Rev 4.2
8/31/98
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 1

1 Page





VSC8111 pdf, ピン配列
Data Sheet
VSC8111
VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 155/622 Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
Receive Section
High speed Non-Return to Zero (NRZ) serial data at 155Mb/s or 622Mb/s are received by the RXDATAIN
inputs. RXDATAIN is clocked in on the rising edge of RXCLKIN+. See Figure 2. The serial data is converted to
byte-wide parallel data and presented on RXOUT[7:0] pins. A divide-by-8 version of the high-speed clock
(RXLSCKOUT) should be used to synchronize the byte-serial RXOUT[7:0] data with the receive portion of the
UNI device.
The receive section also includes frame detection and recovery circuitry which detects the SONET/SDH
frame, aligns the received serial data on byte boundaries, and initiates a frame pulse on FP coincident with the
byte aligned data. The frame recovery is initiated when OOF is held high which must occur at least 4 byte clock
cycles before the A1A2 boundary. The OOF input control is a level-sensitive signal, and the VSC8111 will con-
tinually perform frame detection and recovery as long as this pin is held high even if 1 or more frames has been
detected. Frame detection and recovery occurs when a series of three A1 bytes followed by three A2 bytes has
been detected. The parallel output data on RXOUT[7:0] will be byte aligned starting on the third A2 byte. When
a frame is detected, a single byte clock period long pulse is generated on FP which is synchronized with the
byte-aligned third A2 byte on RXOUT[7:0]. The frame detector sends an FP pulse only if OOF is high or if a
frame was detected while OOF was being pulled low.
Figure 2: Data and Clock Receive Block Diagram
LOSPOL
LOSTTL
RXDATAIN+
RXDATAIN-
RXCLKIN+
RXCLKIN-
0
1
CMU
VSC8111
1:8 Serial
to Parallel
DQ
DQ
DQ
Divide-by-8
RXOUT[7:0]
PM5355
DQ
FP
RXLSCKOUT
DQ
Loss of Signal
During a LOS condition, the VSC8111 forces the receive data low which is an indication for any downstream
equipment that an optical interface failure has occurred. The receive section is clocked by the transmit section’s
G52142-0, Rev 4.2
8/31/98
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 3


3Pages


VSC8111 電子部品, 半導体
VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 155/622 Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
Data Sheet
VSC8111
Loop Timing
LOOPTIM0 mode bypasses the CMU when the LOOPTIM0 input is asserted high. In this mode the CMU
is bypassed by using the receive clock (RXCLKIN), and the entire part is synchronously clocked from a single
external source.
LOOPTIM1 mode bypasses the REFCLK input and uses the divide-by-8 version of the receive clock as the
reference input to the CMU. This mode is selected by asserting the LOOPTIM1 input high. The part is forced
out of this mode if it is in the Loss of Signal state or in Equipment Loopback to prevent the CMU from feeding
its own clock back. The user needs to set the B[0:2] inputs to select 78MHz operation to match the RXLSCK-
OUT frequency.
Clock Multiplier Unit
The VSC8111 uses an integrated phase-locked loop (PLL) for clock synthesis of the 622MHz high speed
clock used for serialization in the transmitter section. The PLL is comprised of a phase-frequency detector
(PFD), an integrating operation amplifier and a voltage controlled oscillator (VCO) configured in classic feed-
back system. The PFD compares the selected divided down version of the 622MHz VCO (select pins B0-B2
select divide-by ratios of 8, 12, 16 and 32, see Table 2) and the reference clock. The integrator provides a trans-
fer function between input phase error and output voltage control. The VCO portion of the PLL is a voltage con-
trolled ring-oscillator with a center frequency of 622MHz.
The reactive elements of the integrator are located off-chip and are connected to the feedback loop of the
amplifier through the CP1, CP2, CN1 and CN2 pins. The configuration of these external surface mounted
capacitors is shown in Figure 6. Table 1 shows the recommended external capacitor values for the configurable
reference frequencies.
Good analog design practices should be applied to the board design for these external components. Tightly
controlled analog ground and power planes should be provided for the PLL portion of the circuitry. The dedi-
cated PLL power (VDDANA) and ground (VSSANA) pins should have quiet supply planes to minimize jitter
generation within the clock synthesis unit. This is accomplished by either using a ferrite bead or a C-L-C choke
(π filter) on the (VDDANA) power pins. Note: Vitesse recommends a (π filter) C-L-C choke over using a ferrite
bead. All ground planes should be tied together using multiple vias.
Table 1: Recommended External Capacitor Values
Reference
Frequency
[MHz]
19.44
38.88
51.84
77.76
Divide Ratio
32
16
12
8
CP
0.1
0.1
0.1
0.1
CN
0.1
0.1
0.1
0.1
Type
X7R
X7R
X7R
X7R
Size
0603/0803
0603/0803
0603/0803
0603/0803
Tol.
+/-10%
+/-10%
+/-10%
+/-10%
Page 6
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52142-0, Rev 4.2
8/31/98

6 Page



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共有リンク

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