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PDF VP536E Data sheet ( Hoja de datos )
| Número de pieza | VP536E | |
| Descripción | NTSC/PAL Digital Video Encoder | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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1 page  
VP536E
Master Reset
The VP536E can be initialized with the RESET pin. This
is an active low signal and must be active for a minimum of 2
CLK12I clock periods in order for the VP536E to be reset.
Video Timing Reset
The VP536E also features the ability to independently
reset the video timing generator without affecting the data
path. The TSURST pin controls this function. Taking this pin
high resets the video timing generator. If this pin is left open,
it is internally pulled low.
CLK12I
HS
VS
RGB/YUV
INPUT DATA
48 Periods
Line 1
Line 2
Line 3
Line 4
Line 17
Fig. 2a. NTSC Input Timing Diagram
Field 1
Line 17
1st
pixel
2nd
pixel
CLK12I
58Periods
HS
VS
RGB/YUV
INPUT DATA
Line 1
Line 2
Line 3
Line 4
Line 23
Fig. 2b. PAL Input Timing Diagram
Field 1
Line 23
1st
pixel
2nd
pixel
NOTE:
1. Coincident falling edges of HS and VS denote the start of an odd field.
2. VS is low during the first 3 lines in each NTSC field and during the first 21/2 lines in each PAL field.
3. Input pixel data is ignored during composite blanking periods.
4
5 Page 
VP536E
AC Characteristics (see note on Page 11)
Parameter
CLK12I clock delay with respect to CLK25I clock
(tested with 50% duty cycle CLK12I and CLK25I clocks)
Data set-up time (wrt CLK12I clock)
Data hold time (wrt CLK12I clock)
HS/VS output delay wrt CLK12I clock
HS low pulse width (NTSC)
HS low pulse width (PAL)
VS low pulse width(NTSC)
VS low pulse width (PAL)
Input clock pulse width high time
Input clock pulse width low time
Analog video output delay (wrt CLK25I clock)
Analog video output rise/fall time
Analog video output settling time (50% to +/- 1 LSB)
Signal related harmonics of DAC outputs for 1MHz.
direct digitally synthesized sine wave
Pipeline delay (data in to analog video out)
VAA supply current
Power supply rejection
(chromacomp, lumacomp = 0.1uF, f = 1 KHz.)
Timing Waveforms
Symbol
tdCLK
tsuDATA
thDATA
tdSYNC
twHS-NTSC
twHS-PAL
twVS-NTSC
twVS-PAL
tdAVO
trfAVO
tsAVO
IAA
Min.
0
8
5
0
16
16
Typ.
59
69
2388
2360
10
8
12
tbd
20.5
200
40
Max.
18
20
Units
ns
ns
ns
ns
CLK12I cycles
CLK12I cycles
CLK12I cycles
CLK12I cycles
ns
ns
ns
ns
ns
dB
CLK12I cycles
mA
dB
CLK25I
CLK12I
RGB
HS/VS
LUMAOUT,
CHROMAOUT,
COMPOUTB
tdCLK
tsuDATA
thDATA
DATA
tdSYNC
ttwwVHSS
Fig. 9. Input/Output Timing Diagram
tdAVO
tsAVO
trfAVO
10
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet VP536E.PDF ] | |
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