|
|
54AC175のメーカーはNational Semiconductorです、この部品の機能は「Quad D Flip-Flop」です。 |
部品番号 | 54AC175 |
| |
部品説明 | Quad D Flip-Flop | ||
メーカ | National Semiconductor | ||
ロゴ | |||
このページの下部にプレビューと54AC175ダウンロード(pdfファイル)リンクがあります。 Total 8 pages
www.DataSheet4U.com
August 1998
54AC175 • 54ACT175
Quad D Flip-Flop
General Description
The ’AC/’ACT175 is a high-speed quad D flip-flop. The de-
vice is useful for general flip-flop requirements where clock
and clear inputs are common. The information on the D in-
puts is stored during the LOW-to-HIGH clock transition. Both
true and complemented outputs of each flip-flop are pro-
vided. A Master Reset input resets all flip-flops, independent
of the Clock or D inputs, when LOW.
n Buffered positive edge-triggered clock
n Asynchronous common reset
n True and complement output
n Outputs source/sink 24 mA
n ’ACT175 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)
— ’AC175: 5962-89552
— ’ACT175: 5962-89693
Features
n Edge-triggered D-type inputs
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP and Flatpak
IEEE/IEC
DS100278-1
DS100278-3
Pin Assignment for LCC
DS100278-2
Pin Names
D0– D3
CP
MR
Q0– Q3
Q0– Q3
Description
Data Inputs
Clock Pulse Input
Master Reset Input
True Outputs
Complement Outputs
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100278
DS100278-4
www.national.com
1 Page Absolute Maximum Ratings (Note 1)
Recommended Operating
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
Junction Temperature (TJ)
CDIP
−0.5V to +7.0V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
±50 mA
±50 mA
−65˚C to +150˚C
175˚C
Conditions
Supply Voltage (VCC)
’AC
2.0V to 6.0V
’ACT
4.5V to 5.5V
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
54AC/ACT
0V to VCC
0V to VCC
−55˚C to +125˚C
Minimum Input Edge Rate (∆V/∆t)
’AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
125 mV/ns
’ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT® circuits outside databook specifications.
DC Characteristics for ’AC Family Devices
Symbol
Parameter
VIH Minimum High Level
Input Voltage
VIL Maximum Low Level
Input Voltage
VOH Minimum High Level
Output Voltage
VOL Maximum Low Level
Output Voltage
IIN
IOLD
IOHD
Maximum Input
Leakage Current
(Note 3)
Minimum Dynamic
Output Current
54AC
VCC
TA = −55˚C to +125˚C
Units
(V) Guaranteed Limits
Conditions
3.0 2.1
4.5 3.15
5.5 3.85
VOUT = 0.1V
V or VCC − 0.1V
3.0 0.9
4.5 1.35
5.5 1.65
VOUT = 0.1V
V or VCC − 0.1V
3.0 2.9
4.5 4.4
IOUT = −50 µA
V
5.5 5.4
3.0 2.4
4.5 3.7
5.5 4.7
3.0 0.1
4.5 0.1
(Note 2)
VIN = VIL or VIH
IOH = −12 mA
V IOH = −24 mA
IOH = −24 mA
IOUT = 50 µA
V
5.5 0.1
(Note 2)
VIN = VIL or VIH
3.0 0.50
IOL = 12 mA
4.5 0.50
V IOL = 24 mA
5.5 0.50
IOL = 24 mA
5.5 ±1.0 µA VI = VCC, GND
5.5 50 mA VOLD = 1.65V Max
5.5 −50 mA VOHD = 3.85V Min
3 www.national.com
3Pages AC Electrical Characteristics
Symbol
Parameter
fmax Maximum Clock
Frequency
tPLH Propagation Delay
CP to Qn or Qn
tPHL Propagation Delay
CP to Qn or Qn
tPLH Propagation Delay
MR to Qn
tPHL Propagation Delay
MR to Qn
Note 10: Voltage Range 5.0 is 5.0V ±0.5V
VCC
(V)
(Note 10)
5.0
5.0
5.0
5.0
5.0
AC Operating Requirements
Symbol
Parameter
ts (H)
ts (L)
th
tw
Setup Time
Dn to CP
Hold Time, HIGH or LOW
Dn to CP
CP Pulse Width
HIGH or LOW
tw MR Pulse Width, LOW
trec Recovery Time, MR to CP
Note 11: Voltage Range 5.0 is 5.0V ±0.5V
VCC
(V)
(Note 11)
5.0
5.0
5.0
5.0
5.0
Capacitance
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation
Capacitance
Typ
4.5
45.0
54ACT
TA = −55˚C to +125˚C
CL = 50 pF
Min Max
95
1.5 11.5
1.5 12.5
1.5 11.5
1.5 11.0
Units
MHz
ns
ns
ns
ns
54ACT
TA = −55˚C to +125˚C
CL = 50 pF
Guaranteed Minimum
3.5
3.5
1.5
5.0
5.0
1.5
Units
ns
ns
ns
ns
ns
Units
pF
pF
Conditions
VCC = OPEN
VCC = 5.0V
Fig.
No.
Fig.
No.
www.national.com
6
6 Page | |||
ページ | 合計 : 8 ページ | ||
|
PDF ダウンロード | [ 54AC175 データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
54AC174 | Hex D Flip-Flop | National Semiconductor |
54AC174 | Hex D Flip-Flop with Master Reset (Rev. A) | Texas Instruments |
54AC175 | Quad D Flip-Flop | National Semiconductor |
54AC175 | 54AC175 54ACT175 Quad D Flip-Flop (Rev. B) | Texas Instruments |