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GS8161E32 の電気的特性と機能

GS8161E32のメーカーはGSIです、この部品の機能は「(GS8161E18 - GS8161E36) Sync Burst SRAMs」です。


製品の詳細 ( Datasheet PDF )

部品番号 GS8161E32
部品説明 (GS8161E18 - GS8161E36) Sync Burst SRAMs
メーカ GSI
ロゴ GSI ロゴ 




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GS8161E32 Datasheet, GS8161E32 PDF,ピン配置, 機能
www.DataSheet4U.com
GS8161E18(T/D)/GS816132(D)/GS816136(T/D)
100-Pin TQFP & 165-Bump BGA 1M x 18, 512K x 32, 512K x 36
Commercial Temp
Industrial Temp
18Mb Sync Burst SRAMs
250 MHz133 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
• FT pin for user-configurable flow through or pipeline
operation
• Dual Cycle Deselect (DCD) operation
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP and 165-bump BGA
packages
Functional Description
Applications
The GS8161E18(T/D)/GS8161E32(D)/GS8161E36(T/D) is a
18,874,368-bit high performance synchronous SRAM with a 2-bit
burst address counter. Although of a type originally developed for
Level 2 Cache applications supporting high performance CPUs, the
device now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control inputs
(ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive-edge-triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the user
via the FT mode pin (Pin 14). Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the Data
Output Register. Holding FT high places the RAM in Pipeline mode,
activating the rising-edge-triggered Data Output Register.
DCD Pipelined Reads
The GS8161E18(T/D)/GS8161E32(D)/GS8161E36(T/D) is a DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. SCD (Single
Cycle Deselect) versions are also available. DCD SRAMs pipeline
disable commands to the same degree as read commands. DCD
RAMs hold the deselect command for one full cycle and then begin
turning off their outputs just after the second rising edge of clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW)
input combined with one or more individual byte write signals (Bx).
In addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS8161E18(T/D)/GS8161E32(D)/GS8161E36(T/D) operates on
a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V
compatible. Separate output power (VDDQ) pins are used to decouple
output noise from the internal circuits and are 3.3 V and 2.5 V
compatible.
Parameter Synopsis
Pipeline
3-1-1-1
3.3 V
2.5 V
Flow Through
2-1-1-1
3.3 V
2.5 V
tKQ
tCycle
Curr (x18)
Curr (x36)
Curr (x18)
Curr (x36)
tKQ
tCycle
Curr (x18)
Curr (x36)
Curr (x18)
Curr (x36)
-250 -225 -200 -166 -150 -133 Unit
2.5 2.7 3.0 3.4 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.7 7.5 ns
280 255 230 200 185 165 mA
330 300 270 230 215 190 mA
275 250 230 195 180 165 mA
320 295 265 225 210 185 mA
5.5 6.0 6.5 7.0 7.5 8.5 ns
5.5 6.0 6.5 7.0 7.5 8.5 ns
175 165 160 150 145 135 mA
200 190 180 170 165 150 mA
175 165 160 150 145 135 mA
200 190 180 170 165 150 mA
Rev: 2.13 11/2004
1/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology

1 Page





GS8161E32 pdf, ピン配列
GS8161E18(T/D)/GS816132(D)/GS816136(T/D)
GS8161E36 100-Pin TQFP Pinout (Package T)
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
FT
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9
10
512K x 36
11 Top View
72
71
70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
Rev: 2.13 11/2004
3/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology


3Pages


GS8161E32 電子部品, 半導体
GS8161E18(T/D)/GS816132(D)/GS816136(T/D)
165 Bump BGA—x32 Common I/O—Top View (Package D)
1 2 3 4 5 6 7 8 9 10 11
A NC A E1 BC BB E3 BW ADSC ADV A NC A
B NC A E2 BD BA CK GW G ADSP A NC B
C NC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC NC C
D DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB D
E DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB E
F DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB F
G DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB G
H FT MCL NC VDD VSS VSS VSS VDD NC ZQ ZZ H
J DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA J
K DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA K
L DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA L
M DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA M
N NC NC VDDQ VSS NC NC NC VSS VDDQ NC NC N
P
NC NC
A
A TDI A1 TDO A
A
A A17
P
R LBO NC A A TMS A0 TCK A A A A
R
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 2.13 11/2004
6/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology

6 Page



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共有リンク

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部品番号部品説明メーカ
GS8161E32

(GS8161E18 - GS8161E36) Sync Burst SRAMs

GSI
GSI
GS8161E32B

(GS8161E18B - GS8161E36B) Sync Burst SRAMs

GSI Technology
GSI Technology
GS8161E36

(GS8161E18 - GS8161E36) Sync Burst SRAMs

GSI
GSI
GS8161E36B

(GS8161E18B - GS8161E36B) Sync Burst SRAMs

GSI Technology
GSI Technology


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