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GS816132B の電気的特性と機能

GS816132BのメーカーはGSIです、この部品の機能は「(GS816118B - GS816136B) Sync Burst SRAMs」です。


製品の詳細 ( Datasheet PDF )

部品番号 GS816132B
部品説明 (GS816118B - GS816136B) Sync Burst SRAMs
メーカ GSI
ロゴ GSI ロゴ 




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GS816132B Datasheet, GS816132B PDF,ピン配置, 機能
www.DataSheet4U.com
GS816118B(T/D)/GS816132B(D)/GS816136B(T/D)
100-Pin TQFP & 165-Bump BGA 1M x 18, 512K x 32, 512K x 36
Commercial Temp
Industrial Temp
18Mb Sync Burst SRAMs
250 MHz150 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP 100-pin TQFP and 165-bump
BGA packages
• RoHS-compliant 100-pin TQFP and 165-bump BGA packages
available
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode pin (Pin 14). Holding the FT mode pin low
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding FT high places the
RAM in Pipeline mode, activating the rising-edge-triggered Data
Output Register.
SCD Pipelined Reads
The GS816118B(T/D)/GS816132B(D)/GS816136B(T/D) is a
SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD
(Dual Cycle Deselect) versions are also available. SCD SRAMs
pipeline deselect commands one stage less than read commands.
SCD RAMs begin turning off their outputs immediately after the
deselect command has been captured in the input registers.
Functional Description
Applications
The GS816118B(T/D)/GS816132B(D)/GS816136B(T/D) is an
18,874,368-bit high performance synchronous SRAM with a 2-bit
burst address counter. Although of a type originally developed for
Level 2 Cache applications supporting high performance CPUs,
the device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip set
support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS816118B(T/D)/GS816132B(D)/GS816136B(T/D)
operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and
2.5 V compatible. Separate output power (VDDQ) pins are used to
decouple output noise from the internal circuits and are 3.3 V and
2.5 V compatible.
Parameter Synopsis
-250 -200 -150 Unit
Pipeline
3-1-1-1
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
2.5 3.0 3.8 ns
4.0 5.0 6.7 ns
295 245 200 mA
345 285 225 mA
Flow Through
2-1-1-1
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
5.5 6.5 7.5 ns
5.5 6.5 7.5 ns
225 200 185 mA
255 220 205 mA
Rev: 1.03 9/2005
1/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology

1 Page





GS816132B pdf, ピン配列
GS816118B(T/D)/GS816132B(D)/GS816136B(T/D)
GS816136B 100-Pin TQFP Pinout
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
FT
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9
10
512K x 36
11 Top View
72
71
70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
Rev: 1.03 9/2005
3/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology


3Pages


GS816132B 電子部品, 半導体
GS816118B(T/D)/GS816132B(D)/GS816136B(T/D)
165 Bump BGA—x32 Common I/O—Top View (Package D)
1 2 3 4 5 6 7 8 9 10 11
A NC A E1 BC BB E3 BW ADSC ADV A NC A
B NC A E2 BD BA CK GW G ADSP A NC B
C NC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC NC C
D DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB D
E DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB E
F DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB F
G DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB G
H FT MCL NC VDD VSS VSS VSS VDD NC NC ZZ H
J DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA J
K DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA K
L DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA L
M DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA M
N NC NC VDDQ VSS NC A NC VSS VDDQ NC NC N
P
NC NC
A
A TDI A1 TDO A
A
A
A
P
R LBO NC A A TMS A0 TCK A A A A
R
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.03 9/2005
6/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology

6 Page



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共有リンク

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部品番号部品説明メーカ
GS816132

(GS816118 - GS816136) Sync Burst SRAMs

GSI
GSI
GS816132B

(GS816118B - GS816136B) Sync Burst SRAMs

GSI
GSI


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