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PDF TSC87C52 Data sheet ( Hoja de datos )
| Número de pieza | TSC87C52 | |
| Descripción | CMOS 0 to 33 MHz Programmable 8-Bit Microcontroller | |
| Fabricantes | TEMIC | |
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TSC87C52
CMOS 0 to 33 MHz Programmable 8–bit Microcontroller
Description
TEMIC’s TSC87C52 is high performance CMOS
EPROM version of the 80C52 CMOS single chip 8 bit
microcontroller.
The fully static design of the TSC87C52 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TSC87C52 retains all the features of the 80C52 with
some enhancement: 8 K bytes of internal code memory
(EPROM); 256 bytes of internal data memory (RAM);
32 I/O lines; three 16 bit timers one with count–down
and clock–out capability; a 6-source, 2-level interrupt
structure; a full duplex serial port with framing error
detection; a power off flag; and an on-chip oscillator.
The TSC87C52 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the RAM, the timers, the serial port and the interrupt
system continue to function. In the power down mode
the RAM is saved and all other functions are inoperative.
The TSC87C52 is manufactured using non volatile
SCMOS process which allows it to run up to:
D 33 MHz with VCC = 5 V ± 10%.
D 16 MHz with 2.7 V < VCC < 5.5 V.
Features
D 8 Kbytes of EPROM
G Improved Quick Pulse programming algorithm
G Secret ROM by encryption
D 256 bytes of RAM
D 64 Kbytes program memory space
D 64 Kbytes data memory space
D 32 programmable I/O lines
D Three 16 bit timer/counters including enhanced
timer 2
D Programmable serial port with framing error
detection
D Power control modes
D Two–level interrupt priority
D Fully static design
D 0.8µ SCMOS non volatile process
D ONCE Mode
D Enhanced Hooks system for emulation purpose
D Available temperature ranges:
G commercial
G industrial
D Available packages:
G PDIP40 (OTP)
G PLCC44 (OTP)
G PQFP44 (OTP)
G CQPJ44 (UV erasable)
G CERDIP40 (UV erasable)
MATRA MHS
Rev. C – 10 Sept 1997
Preliminary
1
1 page  
TSC87C52
Port 3 also serves the functions of various special features of the TEMIC’s C51 Family, as listed below:
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Function
RxD (serial input port)
TxD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (Timer 0 external input)
T1 (Timer 1 external input)
WR (external Data Memory write strobe)
RD (external Data Memory read strobe)
Port 3 can sink/source three LS TTL inputs. It can drive CMOS inputs without external pullups.
Some Port 3 pins receive control signals during EPROM programming and program verification.
RST
A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal pull-down
resistor permits Power-On reset using only a capacitor connected to VCC. The port pins will be driven to their reset
condition when a minimum VIH1 voltage is applied whether the oscillator is started or not (asynchronous reset).
ALE/PROG
Address Latch Enable output for latching the low byte of the address during accesses to external memory. ALE is
activated as though for this purpose at a constant rate of 1/6 the oscillator frequency except during an external data
memory access at which time one ALE pulse is skipped.
ALE can sink/source 8 LS TTL inputs. It can drive CMOS inputs without external pullup.
If desired, to reduce EMI, ALE operation can be disabled by setting bit 0 of SFR location 8Eh (MSCON). With this
bit set, the pin is weakly pulled high. However, ALE remains active during MOVX, MOVC instructions and external
fetches. Setting the ALE disable bit has no effect if the microcontroller is in external execution mode (EA=0).
Throughout the remainder of this datasheet, ALE will refer to the signal coming out of the ALE/PROG pin, and the
pin will be referred to as the ALE/PROG pin.
PSEN
Program Store Enable output is the read strobe to external Program Memory. PSEN is activated twice each machine
cycle during fetches from external Program Memory. (However, when executing out of external Program Memory, two
activations of PSEN are skipped during each access to external Data Memory). PSEN is not activated during fetches
from internal Program Memory. PSEN can sink/source 8 LS TTL inputs. It can drive CMOS inputs without an external
pullup.
EA/VPP
External Access enable. EA must be strapped to VSS in order to enable the device to fetch code from external Program
Memory locations 0000h to FFFFh. Note however, that if any of the Security bits are programmed, EA will be internally
latched on reset.
EA should be strapped to VCC for internal program execution.
This pin also receives the programming supply voltage (VPP) during EPROM programming.
XTAL1
Input to the inverting amplifier that forms the oscillator. Receives the external oscillator signal when an external
oscillator is used.
XTAL2
Output from the inverting amplifier that forms the oscillator. This pin should be floated when an external oscillator
is used.
MATRA MHS
Rev. C – 10 Sept 1997
Preliminary
5
5 Page 
EPROM
TSC87C52
EPROM Structure
The TSC87C52 EPROM is divided in two different arrays:
D the code array:
8 Kbytes.
D the encryption array: 64 bytes.
In addition a third non programmable array is implemented:
D the signature array: 4 bytes.
EPROM Lock System
The program Lock system, when programmed, protects the on–chip program against software piracy.
Encryption Array
Within the EPROM array are 64 bytes of encryption array that are initially unprogrammed (all 1’s). Every time a byte
is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This byte is then
exclusive–NOR’ed (XNOR) with the code byte, creating an encryption verify byte. The algorithm, with the encryption
array in the unprogrammed state, will return the code in its original, unmodified form.
When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying
the byte will produce the encryption byte value. If a large block (>64 bytes) of code left unprogrammed, a verification
routine will display the content of the encryption array. For this reason all the unused code bytes should be programmed
with random values. This will ensure program protection.
EPROM Programming
Set–up modes
In order to program and verify the EPROM or to read the signature bytes, the TSC87C52 is placed in specific set–up
modes (see Figure 8).
Control and program signals must be held at the levels indicated in Table 6.
Definition of terms
Address Lines: P1.0–P1.7, P2.0–P2.4 respectively for A0–A12
Data Lines:
P0.0–P0.7 for D0–D7
Control Signals: RST, PSEN, P2.6, P2.7, P3.3, P3.6, P3.7.
Program Signals: ALE/PROG, EA/VPP.
Table 6 EPROM Set–up Modes
Mode
Program Code data
Verify Code data
Program Encryption Array
Address 0–3Fh
Read Signature Bytes
RST
1
1
1
1
PSEN
0
0
0
0
ALE/
PROG
1
EA/VPP
12.75V
1
12.75V
11
P2.6
0
0
0
0
P2.7
1
1
P3.3
1
0
1
0
P3.6
1
1
0
0
P3.7
1
1
1
0
MATRA MHS
Rev. C – 10 Sept 1997
Preliminary
11
11 Page | ||
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