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PDF NB4N527S Data sheet ( Hoja de datos )
| Número de pieza | NB4N527S | |
| Descripción | Dual AnyLevel to LVDS Receiver/Driver/Buffer/Translator | |
| Fabricantes | ON Semiconductor | |
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NB4N527S
3.3V, 2.5Gb/s Dual
AnyLevel™ to LVDS
Receiver/Driver/Buffer/
Translator with Internal
Input Termination
NB4N527S is a clock or data Receiver/Driver/Buffer/Translator
capable of translating AnyLevelTM input signal (LVPECL, CML,
HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the
distance, noise immunity of the system design, and transmission line
media, this device will receive, drive or translate data or clock signals
up to 2.5 Gb/s or 1.5 GHz, respectively.
The NB4N527S has a wide input common mode range of
GND + 50 mV to VCC − 50 mV combined with two 50 W internal
termination resistors is ideal for translating differential or
single−ended data or clock signals to 350 mV typical LVDS output
levels without use of any additional external components (Figure 6).
The device is offered in a small 3 mm x 3 mm QFN−16 package.
NB4N527S is targeted for data, wireless and telecom applications as
well as high speed logic interface where jitter and package size are
main requirements. Application notes, models, and support
documentation are available on www.onsemi.com.
• Maximum Input Clock Frequency up to 1.5 GHz
• Maximum Input Data Rate up to 2.5 Gb/s (Figure 5)
• 470 ps Maximum Propagation Delay\
• 1 ps Maximum RMS Jitter
• 140 ps Maximum Rise/Fall Times
• Single Power Supply; VCC = 3.3 V $10%
• Temperature Compensated TIA/EIA−644 Compliant LVDS Outputs
• Internal 50 W Termination Resistor per Input Pin
• GND + 50 mV to VCC − 50 mV VCMR Range
• Pb−Free Packages are Available
Device DDJ = 10 ps
http://onsemi.com
1
QFN−16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB4N
527S
ALYW G
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
VTD0
D0
D0
VTD0
50 W*
50 W*
Q0
Q0
VTD1
D1
D1
VTD1
50 W*
50 W*
Q1
Q1
Figure 1. Functional Block Diagram
*RTIN
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 223−1 (VINPP = 400 mV; Input Signal DDJ = 14 ps)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 3
1
Publication Order Number:
NB4N527S/D
1 page  
NB4N527S
Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; (Note 10)
−40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
VOUTPP Output Voltage Amplitude (@ VINPPmin) fin ≤ 1.0 GHz 220 350
(Figure 4)
fin= 1.5 GHz 200 300
220 350
200 300
220 350
200 300
mV
fDATA Maximum Operating Data Rate
1.5 2.5
1.5 2.5
1.5 2.5
Gb/s
tPLH,
tPHL
Differential Input to Differential Output
Propagation Delay
270 370 470 270 370 470 270 370 470 ps
tSKEW
Duty Cycle Skew (Note 11)
Within Device Skew (Note 17)
Device−to−Device Skew (Note 15)
8 45
5 25
30 100
8 45
5 25
30 100
8 45 ps
5 25
30 100
tJITTER
RMS Random Clock Jitter (Note 13) fin = 1.0 GHz
fin = 1.5 GHz
Deterministic Jitter (Note 14) fDATA = 622 Mb/s
fDATA = 1.5 Gb/s
fDATA = 2.488 Gb/s
Crosstalk Induced Jitter (Note 16)
0.5 1
0.5 1
6 20
7 20
10 25
20 40
0.5 1
0.5 1
6 20
7 20
10 25
20 40
0.5 1
0.5 1
6 20
7 20
10 25
20 40
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 12)
100 VCC− 100 VCC− 100 VCC− mV
GND
GND
GND
tr Output Rise/Fall Times @ 250 MHz
tf (20% − 80%)
Q, Q 60 100 140 60 100 140 60 100 140 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10. Measured by forcing VINPPmin with 50% duty cycle clock source and VCC − 1400 mV offset. All loading with an external RL = 100 W across
“D” and “D” of the receiver. Input edge rates 150 ps (20%−80%).
11. See Figure 13 differential measurement of tskew = |tPLH − tPHL| for a nominal 50% differential clock input waveform @ 250 MHz.
12. Input voltage swing is a single−ended measurement operating in differential mode.
13. RMS jitter with 50% duty cycle input clock signal.
14. Deterministic jitter with input NRZ data at PRBS 223−1 and K28.5.
15. Skew is measured between outputs under identical transition @ 250 MHz.
16. Crosstalk induced jitter is the additive deterministic jitter to channel one with channel two active both running at 622 Gb/s PRBS 223 −1 as
an asynchronous signals.
17. The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition.
400
350
300
−40°C
250
200 85°C
25°C
150
100
50
0
0 0.5 1 1.5 2 2.5 3
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) and Temperature (@ VCC = 3.3 V)
http://onsemi.com
5
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