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LC78605E PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 LC78605E
部品説明 Compact Disc Player DSP
メーカ Sanyo Semicon Device
ロゴ Sanyo Semicon Device ロゴ 

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LC78605E Datasheet, LC78605E PDF,ピン配置, 機能
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Ordering number : ENN7735
SANYO Semiconductors
DATA SHEET
CMOS IC
LC78605E Compact Disc Player DSP with
Built-in Microcontroller
Overview
The LC78605E CMOS IC implements the signal processing, servo control, LCD display, button state acquisition, and
remote controller handling required by compact disc players without requiring a separate microcontroller. It provides
the following basic functions: demodulation of the EFM signal from the optical pickup, deinterleaving, error detection
and correction, 8× oversampling audio filters, D/A converter (with built-in analog low-pass filter), LCD display drivers,
key acquisition (A/D) and control processing, and automatic discrimination and playback of CD-RW discs. Thus the
LC78604E is ideal for implementing low-end CD players that support playback of CD-RW discs.
The LC78604E also provides a radio tuner frequency display function, and allows digital display of the selected
frequency in manual tuning CD radio/cassette players.
Functions
• Implements the CD play/pause, stop, track selection, fast forward/fast rewind, repeat 1/repeat all, program
setup/play/clear for up to 30 tracks, and shuffle play functions controlled from CD player buttons.
<Signal-Processing Block>
• The signal-processing block applies slicing at the correct level to the input HF signal, and converts that signal to an
EFM signal. At the same time it generates a PLL clock signal with an average frequency of 4.3218MHz by
comparing the phase with that of the internal VCO.
• A reference clock signal and all necessary timings can be generated using an external 16.9344MHz crystal.
• The disc motor speed is controlled by a frame phase difference signal created from the playback clock and the
reference clock.
• Performs frame sync signal detection, protection, and interpolation to assure stable data readout.
• Demodulates the EFM signal and converts the result to 8-bit symbol data.
• Separates the subcode data from the EFM signal and outputs that data to the internal control processing block.
• After applying a CRC check to the subcode Q data, outputs that data to the internal control processing block.
• Buffers the demodulated EFM signal in internal RAM and compensates for up to ±4 frames of jitter due to
fluctuations in the disc speed.
• Applies unscrambling and deinterleaving to the demodulated EFM signal in the stipulated order.
• Performs error detection, correction, and flag processing (C1: double, C2: double).
• Sets the C2 flags according to the C1 flags and the C2 check and applies interpolation and previous value hold
processing to the output signal according to the C2 flags. This interpolation circuit implements 2-value
interpolation. A previous value hold operation is applied if the C2 flags indicate errors for over 2 consecutive
samples.
• The internal control processing block controls the track jump, focus start, disc motor start/stop, muting on/off, track
count, and other operations.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
32504TN (OT) No.7735-1/11

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