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PDF S30MS-P Data sheet ( Hoja de datos )
| Número de pieza | S30MS-P | |
| Descripción | NAND Interface Memory Based | |
| Fabricantes | SPANSION | |
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S30MS-P ORNANDTMFlash Family
S30MS01GP, S30MS512P
1Gb/512Mb, x8/x16, 1.8 Volt NAND Interface Memory Based on
MirrorBit™ Technology
Data Sheet (Preliminary)
S30MS-P ORNANDTMFlash Family Cover Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S30MS-P_00
Revision A Amendment 7
Issue Date August 4, 2006
1 page  
Data Sheet (Preliminary)
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Table 11.1
Table 11.2
Table 11.3
Table 12.1
Table 12.2
Memory Addressing Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
(1Gb) x 8 device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
(512Mb) x8 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
(1Gb) x 16 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
(512) x 16 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Read Mode Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Page Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Status Output Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figures
Figure 9.1 Command Input Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9.2 Address Input Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9.3 Data Input Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9.4 Serial Read Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9.5 Status Read Cycle Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9.6 Read Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9.7 Column Address Change in Read Cycle Timing Diagram (1/2). . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9.8 Column Address Change in Read Cycle Timing Diagram (2/2). . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9.9 Program Operation Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9.10 Block Erase Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9.11 Cache Program Operation Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9.12 Page Duplicate Program Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9.13 ID Read Operation Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10.1 Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12.1 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 12.2 Column Address Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 12.3 Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 12.4 Serial Input Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 12.5 Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 12.6 Page Duplicate Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 12.7 Page Duplicate Program Operation with Random Data Input . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 12.8 Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 12.9 Multiple Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 12.10 Status Read Timing Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 12.11 Reset (FFh) Command Input During Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 12.12 Reset (FFh) Command Input During Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 12.13 Reset (FFh) Command Input During a Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 12.14 Reset (FFh) Command During Operations Other Than Program, Erase, or Read . . . . . . . . 32
Figure 12.15 Status Read Command (70h) Input After a Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 13.1 Power-On/Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 13.2 Power-On Auto-read Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 13.3 Status Read During a Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 13.4 RY/BY#: Termination for the Ready/Busy Pin (RY/BY#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 13.5 WP# Signal—Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
3
5 Page 
Data Sheet (Preliminary)
4. Pin Names and Descriptions
4.1
Pin Names and Functions
Pin Name
I/O0 to I/O15
CLE
ALE
CE#, CE1#, CE2#
RE#
WE#
WP#
PRE
RY/BY#
VCC
VSS
N.C.
Pin Function
Data Input/Output
Command Latch Enable
Address Latch Enable
Chip Enable
Read Enable
Write Enable
Write Protect
Power on Read Enable
Ready/Busy Output
Power
Ground
No Connection
4.2
Pin Descriptions
The device is a byte/word serial access memory that utilizes time-sharing input of address information. The
device pin-outs are configured as shown in 137-Ball MS01GP MCP-Compatible FBGA Pinout on page 5.
CLE
Pin
ALE
CE#, CE1#, CE2#
WE#
RE#
I/O0 to I/O7
I/O8 to I/O15
WP#
RY/BY#
PRE
VSS
N.C
Description
Command Latch Enable: The CLE input signal is used to control loading of the operation mode command into
the internal command register. The command is latched into the command register from the I/O port on the
rising edge of the WE# signal while CE# is low and CLE is High.
Address Latch Enable: The ALE signal is used to control loading of either address information or input data
into the internal address/data register. Address information is latched on the rising edge of WE# if CE# is low
and ALE is High.
Input data is latched if CE# is low and ALE is Low.
Chip Enable: The device enters a low-power Standby mode when the device is in Ready mode. The CE#
signal is ignored when the device is in a Busy state (RY/BY# = L), such as during a Page Buffer Load or Erase
operation, and will not enter Standby mode even if the CE# input goes high. The CE# signal may be inactive
during the Page Buffer write and Page Buffer load of the array data. The 2Gb device has two chip enable pins:
CE1# and CE2# (one per die).
Write Enable: The WE# signal is used to control the acquisition of data from the I/O port.
Read Enable: The RE# signal controls serial data output. Data is available tREA after the falling edge of RE#.
The internal column address counter is also incremented (Address = Address + 1) on this falling edge.
I/O Port: The I/O0 to I/O7 pins are used as a port for transferring address, command, and input/output data to
and from the device.
I/O Port: The I/O8 to I/O15 pins are used as a port for transferring input/output data to and from the device in
x16 mode only. I/O8 to I/O15 pins must be low level during address and command input.
Write Protect: The WP# signal is used to protect the device from accidental programming or erasing. This
signal is usually used for protecting the data during the power-on/off sequence when input signals are invalid.
Ready/Busy:The RY/BY# output signal is used to indicate the operating condition of the device. The RY/BY#
signal is in Busy state (RY/BY# = L) during the Program, Erase, and Read operations and return to Ready state
(RY/BY# = H) after completion of the operation. The output buffer for this signal is an open drain.
Power-on Read Enable: The PRE controls auto read operation executed during power-on. The power-on auto-
read is enabled when PRE pin in tied to VCC.
Ground: VSS is the Ground.
No Connection: Lead is not internally connected.
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
9
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet S30MS-P.PDF ] | |
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