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S29WS128N の電気的特性と機能

S29WS128NのメーカーはSPANSIONです、この部品の機能は「Burst Mode Flash Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 S29WS128N
部品説明 Burst Mode Flash Memory
メーカ SPANSION
ロゴ SPANSION ロゴ 




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S29WS128N Datasheet, S29WS128N PDF,ピン配置, 機能
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S29WSxxxN MirrorBit™ Flash Family
S29WS256N, S29WS128N, S29WS064N
256/128/64 Megabit (16/8/4 M x 16-Bit) CMOS 1.8 Volt-only
Simultaneous Read/Write, Burst Mode Flash Memory
Data Sheet
General Description
PRELIMINARY
The Spansion S29WS256/128/064N are MirrorbitTM Flash products fabricated on 110 nm process technology. These burst
mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate
banks using separate data and address pins. They operate up to 80 MHz and use a single VCC of 1.7–1.95 volts that
makes them ideal for today’s demanding wireless applications requiring higher density, better performance and lowered
power consumption.
Distinctive Characteristics
„ Single 1.8 V read/program/erase (1.70–1.95 V)
„ 110 nm MirrorBit™ Technology
„ Simultaneous Read/Write operation with zero
latency
„ 32-word Write Buffer
„ Sixteen-bank architecture consisting of 16/8/4
Mbit for WS256N/128N/064N, respectively
„ Four 16 Kword sectors at both top and bottom of
memory array
„ 254/126/62 64 Kword sectors (WS256N/128N/
064N)
„ Programmable burst read modes
— Linear for 32, 16 or 8 words linear read with or
without wrap-around
— Continuous sequential read mode
„ SecSi™ (Secured Silicon) Sector region consisting
of 128 words each for factory and customer
„ 20-year data retention (typical)
„ Cycling Endurance: 100,000 cycles per sector
(typical)
„ RDY output indicates data available to system
„ Command set compatible with JEDEC standards
„ Hardware (WP#) protection of top and bottom
sectors
„ Dual boot sector configuration (top and bottom)
„ Offered Packages
— WS064N: 80-ball FBGA (7 mm x 9 mm)
— WS256N/128N: 84-ball FBGA (8 mm x 11.6 mm)
„ Low VCC write inhibit
„ Persistent and Password methods of Advanced
Sector Protection
„ Write operation status bits indicate program and
erase operation completion
„ Suspend and Resume commands for Program and
Erase operations
„ Unlock Bypass program command to reduce
programming time
„ Synchronous or Asynchronous program operation,
independent of burst control register settings
„ ACC input pin to reduce factory programming time
„ Support for Common Flash Interface (CFI)
„ Industrial Temperature range (contact factory)
Performance Characteristics
Read Access Times
Speed Option (MHz)
80
Max. Synch. Latency, ns (tIACC)
Max. Synch. Burst Access, ns (tBACC)
Max. Asynch. Access Time, ns (tACC)
Max CE# Access Time, ns (tCE)
Max OE# Access Time, ns (tOE)
69
9
70
70
11.2
66
69
11.2
70
70
11.2
54
69
13.5
70
70
13.5
Current Consumption (typical values)
Continuous Burst Read @ 66 MHz
Simultaneous Operation (asynchronous)
Program (asynchronous)
Erase (asynchronous)
Standby Mode (asynchronous)
35 mA
50 mA
19 mA
19 mA
20 µA
Typical Program & Erase Times
Single Word Programming
Effective Write Buffer Programming (VCC) Per Word
Effective Write Buffer Programming (VACC) Per Word
Sector Erase (16 Kword Sector)
Sector Erase (64 Kword Sector)
40 µs
9.4 µs
6 µs
150 ms
600 ms
Publication Number S29WSxxxN_00 Revision F Amendment 0 Issue Date October 29, 2004

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S29WS128N pdf, ピン配列
Preliminary
List of Figures
Figure 4.2. VBH084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm MCP Compatible Package .......................................................... 10
Figure 4.3. 80-ball Fine-Pitch Ball Grid Array (S29WS064N) .................................................................................................................... 11
Figure 4.4. TLC080—80-ball Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm MCP Compatible Package ............................................................... 12
Figure 4.5. MCP Look-ahead Diagram ................................................................................................................................................... 14
Figure 7.2. Synchronous Read ............................................................................................................................................................. 24
Figure 7.19. Single Word Program....................................................................................................................................................... 30
Figure 7.22. Write Buffer Programming Operation ................................................................................................................................. 34
Figure 7.24. Sector Erase Operation.................................................................................................................................................... 37
Figure 7.33. Write Operation Status Flowchart ...................................................................................................................................... 44
Figure 8.2. Lock Register Program Algorithm ......................................................................................................................................... 55
Figure 11.2. Maximum Positive Overshoot Waveform.............................................................................................................................. 62
Figure 11.3. Test Setup ...................................................................................................................................................................... 63
Figure 11.4. Input Waveforms and Measurement Levels.......................................................................................................................... 64
Figure 11.5. VCC Power-up Diagram ..................................................................................................................................................... 64
Figure 11.6. CLK Characterization ........................................................................................................................................................ 66
Figure 11.7. CLK Synchronous Burst Mode Read .................................................................................................................................... 68
Figure 11.8. 8-word Linear Burst with Wrap Around ............................................................................................................................... 69
Figure 11.9. 8-word Linear Burst without Wrap Around ........................................................................................................................... 69
Figure 11.10. Linear Burst with RDY Set One Cycle Before Data ............................................................................................................... 70
Figure 11.11. Asynchronous Mode Read................................................................................................................................................ 71
Figure 11.12. Reset Timings................................................................................................................................................................ 72
Figure 11.2. Chip/Sector Erase Operation Timings: WE# Latched Addresses ............................................................................................. 74
Figure 11.13. Asynchronous Program Operation Timings: WE# Latched Addresses ..................................................................................... 75
Figure 11.14. Synchronous Program Operation Timings: CLK Latched Addresses ........................................................................................ 76
Figure 11.15. Accelerated Unlock Bypass Programming Timing ................................................................................................................ 77
Figure 11.16. Data# Polling Timings (During Embedded Algorithm) .......................................................................................................... 77
Figure 11.17. Toggle Bit Timings (During Embedded Algorithm) ............................................................................................................... 78
Figure 11.18. Synchronous Data Polling Timings/Toggle Bit Timings ......................................................................................................... 78
Figure 11.19. DQ2 vs. DQ6 ................................................................................................................................................................. 79
Figure 11.20. Latency with Boundary Crossing when Frequency > 66 MHz................................................................................................. 79
Figure 11.21. Latency with Boundary Crossing into Program/Erase Bank ................................................................................................... 80
Figure 11.22. Example of Wait States Insertion ..................................................................................................................................... 81
Figure 11.23. Back-to-Back Read/Write Cycle Timings ............................................................................................................................ 82
October 29, 2004 S29WSxxxN_00_F0
S29WSxxxN MirrorBit™ Flash Family
3


3Pages


S29WS128N 電子部品, 半導体
Preliminary
2 Input/Output Descriptions & Logic Symbol
Table identifies the input and output package connections provided on the device.
Symbol
A23–A0
DQ15–DQ0
CE#
OE#
WE#
VCC
VIO
VSS
NC
RDY
CLK
AVD#
RESET#
WP#
ACC
RFU
Table 2.1. Input/Output Descriptions
Type
Description
Input
Address lines for WS256N (A22-A0 for WS128 and A21-A0 for WS064N).
I/O Data input/output.
Input
Input
Chip Enable. Asynchronous relative to CLK.
Output Enable. Asynchronous relative to CLK.
Input
Write Enable.
Supply
Device Power Supply.
Input
I/O
VersatileIO Input. Should be tied to VCC.
Ground.
No Connect Not connected internally.
Output
Ready. Indicates when valid burst data is ready to be read.
Input
Clock Input. In burst mode, after the initial word is output, subsequent active edges of CLK
increment the internal address counter. Should be at VIL or VIH while in asynchronous
mode.
Input
Address Valid. Indicates to device that the valid address is present on the address inputs.
When low during asynchronous mode, indicates valid address; when low during burst
mode, causes starting address to be latched at the next active clock edge.
When high, device ignores address inputs.
Input
Hardware Reset. Low = device resets and returns to reading array data.
Input
Input
Write Protect. At VIL, disables program and erase functions in the four outermost sectors.
Should be at VIH for all other conditions.
Acceleration Input. At VHH, accelerates programming; automatically places device in
unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for
all other conditions.
Reserved Reserved for future use (see MCP look-ahead pinout for use with MCP).
6
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_00_F0 October 29, 2004

6 Page



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共有リンク

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部品番号部品説明メーカ
S29WS128J

(S29WS064J / S29WS128J) Burst Mode Flash Memory

SPANSION
SPANSION
S29WS128N

SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY

SPANSION
SPANSION
S29WS128N

Burst Mode Flash Memory

SPANSION
SPANSION
S29WS128P

Simultaneous Read/Write Flash

Cypress Semiconductor
Cypress Semiconductor


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