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S29PL127N の電気的特性と機能

S29PL127NのメーカーはSPANSIONです、この部品の機能は「Page-Mode Flash Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 S29PL127N
部品説明 Page-Mode Flash Memory
メーカ SPANSION
ロゴ SPANSION ロゴ 




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S29PL127N Datasheet, S29PL127N PDF,ピン配置, 機能
www.DataSheet4U.com
S29PL-N MirrorBit™ Flash Family
29PL256N, S29PL127N, S29PL129N,
256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only
Simultaneous Read/Write, Page-Mode Flash Memory
Data Sheet
PRELIMINARY
Notice to Readers: This document indicates states the current technical
specifications regarding the Spansion product(s) described herein. The
Preliminary status of this document indicates that a product qualification has
been completed, and that initial production has begun. Due to the phases of
the manufacturing process that require maintaining efficiency and quality, this
document may be revised by subsequent versions or modifications due to
changes in technical specifications.
Publication Number S29PL-N_00 Revision A Amendment 4 Issue Date November 23, 2005

1 Page





S29PL127N pdf, ピン配列
S29PL-N MirrorBit™ Flash Family
S29PL256N, S29PL127N, S29PL129N,
256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only
Simultaneous Read/Write, Page-Mode Flash Memory
Data Sheet
PRELIMINARY
General Description
The Spansion S29PL-N is the latest generation 3.0-Volt page mode read family fabricated using the 110 nm MirrorbitTM
Flash process technology. These 8-word page-mode Flash devices are capable of performing simultaneous read and write
operations with zero latency on two separate banks. These devices offer fast page access times of 25 to 30 ns, with
corresponding random access times of 65 ns, 70 ns, and 80 ns respectively, allowing high speed microprocessors to op-
erate without wait states. The S29PL129N device offers the additional feature of dual chip enable inputs (CE1# and
CE2#) that allow each half of the memory space to be controlled separately.
Distinctive Characteristics
Architectural Advantages
Hardware Features
„ 32-Word Write Buffer
„ Dual Chip Enable Inputs (only for S29PL129N)
— Two CE# inputs control selection of each half of the
memory space
„ Single Power Supply Operation
— Full Voltage range of 2.7 – 3.6 V read, erase, and
program operations for battery-powered applications
— Voltage range of 2.7 – 3.1 V valid for PL-N MCP
products
„ Simultaneous Read/Write Operation
— Data can be continuously read from one bank while
executing erase/program functions in another bank
— Zero latency switching from write to read operations
„ 4-Bank Sector Architecture with Top and Bottom
Boot Blocks
„ 256-Word Secured Silicon Sector Region
— Up to 128 factory-locked words
— Up to 128 customer-lockable words
„ Manufactured on 0.11 µm Process Technology
„ Data Retention of 20 years Typical
„ Cycling Endurance of 100,000 Cycles per Sector
Typical
Performance Characteristics
„ WP#/ACC (Write Protect/Acceleration) Input
— At VIL, hardware level protection for the first and last
two 32 Kword sectors.
— At VIH, allows the use of DYB/PPB sector protection
— At VHH, provides accelerated programming in a
factory setting
„ Dual Boot and No Boot Options
„ Low VCC Write Inhibit
Security Features
„ Persistent Sector Protection
— A command sector protection method to lock
combinations of individual sectors to prevent
program or erase operations within that sector
— Sectors can be locked and unlocked in-system at VCC
level
„ Password Sector Protection
— A sophisticated sector protection method locks
combinations of individual sectors to prevent program
or erase operations within that sector using a user
defined 64-bit password
Read Access Times (@ 30 pF, Industrial Temp.)
Random Access Time, ns (tACC)
Page Access Time, ns (tPACC)
Max CE# Access Time, ns (tCE)
Max OE# Access Time, ns (tOE)
65 70
25 30
65 70
25 30
80
30
80
30
Current Consumption (typical values)
8-Word Page Read
Simultaneous Read/Write
Program/Erase
Standby
6 mA
65 mA
25 mA
20 µA
Typical Program & Erase Times (typical values) (See Note)
Typical Word
40 µs
Typical Effective Word (32 words in buffer)
9.4 µs
Accelerated Write Buffer Program
6 µs
Typical Sector Erase Time (32-Kword Sector)
300 ms
Typical Sector Erase Time (128-Kword Sector)
1.6 s
Note: : Typical program and erase times assume the following
conditions: 25°C, 3.0 V VCC, 10,000 cycles; checkerboard data pattern.
Package Options
S29PL-N
VBH064
8.0 x 11.6 mm,
64-ball
VBH084
8.0 x 11.6 mm,
84-ball
LAA064
11 x 13 mm, 64-ball
Fortified BGA
256 „ „
129 „
127 „
„
Publication Number S29PL-N_00 Revision A Amendment 4 Issue Date November 23, 2005


3Pages


S29PL127N 電子部品, 半導体
Preliminary
Tables
Table 2.1
Table 6.1
Table 6.2
Table 6.3
Table 7.1
Table 7.2
Table 7.3
Table 7.4
Table 7.5
Table 7.6
Table 7.7
Table 7.8
Table 7.9
Table 7.10
Table 7.11
Table 7.12
Table 7.13
Table 7.14
Table 7.15
Table 7.16
Table 7.17
Table 7.18
Table 7.19
Table 8.1
Table 8.2
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 11.1
Table 12.1
Table 12.2
Table 12.3
Table 12.4
Table 12.5
Table 12.6
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PL256N Sector and Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PL127N Sector and Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PL129N Sector and Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Dual Chip Enable Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Word Selection within a Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Autoselect Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Autoselect Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Autoselect Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Single Word Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Write Buffer Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Sector Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Program Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Program Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Unlock Bypass Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Unlock Bypass Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Unlock Bypass Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Sector Protection Schemes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Secured Silicon Sector Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Secured Silicon Sector Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Secured Silicon Sector Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Secured Silicon Sector Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Memory Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Sector Protection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
System Interface String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005

6 Page



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共有リンク

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部品番号部品説明メーカ
S29PL127H

Multi-chip Products (MCP)

Advanced Micro Devices
Advanced Micro Devices
S29PL127J

Page Mode and Simultaneous Read/Write Flash memory device

Cypress Semiconductor
Cypress Semiconductor
S29PL127J

Simultaneous-Read/Write Flash Memory

SPANSION
SPANSION
S29PL127N

Page-Mode Flash Memory

SPANSION
SPANSION


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