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S29NS016J の電気的特性と機能

S29NS016JのメーカーはSPANSIONです、この部品の機能は「Burst Mode Flash Memories」です。


製品の詳細 ( Datasheet PDF )

部品番号 S29NS016J
部品説明 Burst Mode Flash Memories
メーカ SPANSION
ロゴ SPANSION ロゴ 




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S29NS016J Datasheet, S29NS016J PDF,ピン配置, 機能
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S29NS-J
128 Megabit (8 M x 16-Bit), 64 Megabit (4 M x 16-Bit),
32 Megabit (2 M x 16-Bit), and 16 Megabit (1 M x 16 Bit),
110 nm CMOS 1.8-Volt only Simultaneous Read/Write,
Burst Mode Flash Memories
Data Sheet
Notice to Readers: This document states the current technical specifications
regarding the Spansion product(s) described herein. Spansion LLC deems the
products to have been in sufficient production volume such that subsequent
versions of this document are not expected to change. However, typographical
or specification corrections, or modifications to the valid combinations offered
may occur.
Publication Number S29NS-J_01 Revision A Amendment 10 Issue Date March 22, 2006

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S29NS016J pdf, ピン配列
Data Sheet
Table Of Contents
Notice On Data Sheet Designations . . . . . . . . . . . ii
Advance Information .......................................................................................ii
Preliminary ..........................................................................................................ii
Combination .......................................................................................................ii
Full Production (No Designation on Document) ...................................ii
Simultaneous Read/Write Operations with Zero Latency ......................2
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram of Simultaneous Operation Circuit
5
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 12
Valid Combinations .............................................................................................13
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 14
Table 1. Device Bus Operations ........................................... 14
Requirements for Asynchronous Read Operation (Non-Burst) .......... 14
Requirements for Synchronous (Burst) Read Operation ....................... 14
Continuous Burst .............................................................................................15
8-, 16-, and 32-Word Linear Burst with Wrap Around .......................15
Table 2. Burst Address Groups ............................................ 16
8-, 16-, and 32-Word Linear Burst without Wrap Around ................ 16
Programmable Wait State ................................................................................ 16
Handshaking Feature ......................................................................................17
Simultaneous Read/Write Operations with Zero Latency .....................17
Writing Commands/Command Sequences ..................................................17
Accelerated Program Operation ................................................................17
Autoselect Functions ......................................................................................17
Standby Mode ........................................................................................................17
Automatic Sleep Mode ...................................................................................... 18
RESET#: Hardware Reset Input ..................................................................... 18
VCC Power-up and Power-down Sequencing ........................................ 18
Output Disable Mode ........................................................................................ 18
Hardware Data Protection .............................................................................. 18
WP# Boot Sector Protection ......................................................................... 19
Low VCC Write Inhibit ................................................................................ 19
Write Pulse “Glitch” Protection ................................................................ 19
Logical Inhibit ................................................................................................... 19
Common Flash Memory Interface (CFI) . . . . . . 20
Table 3. CFI Query Identification String ................................ 20
Table 4. System Interface String ......................................... 20
Table 5. Device Geometry Definition .................................... 21
Table 6. Primary Vendor-Specific Extended Query ................. 21
Table 7. Sector Address Table, S29NS128J ........................... 23
Table 8. Sector Address Table, S29NS064J ........................... 27
Table 9. Sector Address Table, S29NS032J ........................... 31
Table 10. Sector Address Table, S29NS016J ......................... 32
Command Definitions ........................................................................................33
Reading Array Data ............................................................................................33
Set Configuration Register Command Sequence ......................................34
Table 11. Burst Modes ....................................................... 34
Handshaking Feature .....................................................................................34
Table 12. Wait States for Handshaking ................................. 35
Sector Lock/Unlock Command Sequence ...................................................35
Reset Command ..................................................................................................35
Autoselect Command Sequence ....................................................................36
Table 13. Autoselect Device ID ............................................ 36
Program Command Sequence ........................................................................36
Unlock Bypass Command Sequence .........................................................37
Figure 1. Program Operation ............................................... 38
Chip Erase Command Sequence ................................................................... 38
Sector Erase Command Sequence ................................................................ 39
Accelerated Sector Group Erase .............................................................. 39
Table 14. Accelerated Sector Erase Groups, S29NS128J ......... 40
Table 15. Accelerated Sector Erase Groups, S29NS064J ......... 40
Table 16. Accelerated Sector Erase Groups, S29NS032J ......... 41
Table 17. Accelerated Sector Erase Groups, S29NS016J ......... 41
Erase Suspend/Erase Resume Commands .................................................. 42
Figure 2. Erase Operation ................................................... 43
Table 18. Command Definitions .......................................... 44
DQ7: Data# Polling ............................................................................................ 45
Figure 3. Data# Polling Algorithm ........................................ 46
RDY: Ready ...........................................................................................................47
DQ6: Toggle Bit I ............................................................................................... 47
DQ2: Toggle Bit II .............................................................................................. 47
Figure 4. Toggle Bit Algorithm ............................................. 48
Table 19. DQ6 and DQ2 Indications ..................................... 49
Reading Toggle Bits DQ6/DQ2 .....................................................................49
DQ5: Exceeded Timing Limits ........................................................................49
DQ3: Sector Erase Timer ................................................................................50
Table 20. Write Operation Status ......................................... 50
Figure 5. Maximum Negative Overshoot Waveform ................ 51
Figure 6. Maximum Positive Overshoot Waveform.................. 51
Operating Ranges ................................................................................................ 51
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 52
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 7. Test Setup .......................................................... 53
Table 21. Test Specifications ............................................... 53
Key to Switching Waveforms . . . . . . . . . . . . . . . 53
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 53
Figure 8. Input Waveforms and Measurement Levels.............. 53
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 54
VCC Power-up ..................................................................................................... 54
Figure 9. VCC Power-up Diagram.......................................... 54
CLK Characterization ....................................................................................... 55
Figure 10. CLK Characterization........................................... 55
Synchronous/Burst Read .................................................................................. 56
Figure 11. Burst Mode Read (66 and 54 MHz)........................ 56
Figure 12. Burst Mode Read (40 MHz) .................................. 57
Asynchronous Read ........................................................................................... 58
Figure 13. Asynchronous Mode Read .................................... 58
Figure 14. Reset Timings .................................................... 59
Erase/Program Operations ..............................................................................60
Figure 15. Program Operation Timings ................................. 61
Figure 16. Chip/Sector Erase Operations............................... 62
Figure 17. Accelerated Unlock Bypass Programming Timing..... 63
Figure 18. Data# Polling Timings (During Embedded Algorithm) ...
64
Figure 19. Toggle Bit Timings (During Embedded Algorithm) ... 64
Figure 20. 8-, 16-, and 32-Word Linear Burst Address Wrap Around
65
Figure 21. Latency with Boundary Crossing ........................... 65
Figure 22. Initial Access at 3Eh with Address Boundary Latency 66
Figure 23. Example of Extended Valid Address Reducing Wait State
Usage .............................................................................. 66
Figure 24. Back-to-Back Read/Write Cycle Timings ................ 67
BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 68
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 69
S29NS128J ..............................................................................................................69
VDC048—48-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 10 x
March 22, 2006 S29NS-J_01_A10
S29NS-J
iii


3Pages


S29NS016J 電子部品, 半導体
Data Sheet
General Description
The S29NS128J, S29NS064J, S29NS032J and S29NS016J are 128 Mbit, 64 Mbit, 32 Mbit and 16
Mbit 1.8 Volt-only, Simultaneous Read/Write, Burst Mode Flash memory devices, organized as
8,388,608, 4,194,304, 2,097,152 and 1,048,576. words of 16 bits each. These devices use a sin-
gle VCC of 1.7 to 1.95 V to read, program, and erase the memory array. A 12.0-volt Acc may be
used for faster program performance if desired. These devices can also be programmed in stan-
dard EPROM programmers.
The devices are offered at the following speeds:
Clock
Speed
Burst Access (ns)
Synch. Initial Access
(ns)
Asynchronous Initial
Access (ns)
Output
Loading
66 MHz
54 MHz
11
13.5
71
87.5
65
30 pF
70
The devices operate within the temperature range of –25 °C to +85 °C, and are offered Very Thin
FBGA packages.
Simultaneous Read/Write Operations with Zero Latency
The Simultaneous Read/Write architecture divides the memory space into four banks. The device
allows a host system to program or erase in one bank, then immediately and simultaneously read
from another bank, with zero latency. This releases the system from waiting for the completion
of program or erase operations.
The devices are structured as shown in the following tables:
Bank A Sectors
Quantity
Size
S29NS128J
Bank B, C & D Sectors
Quantity
Size
4 8 Kwords
63 32 Kwords
32 Mbits total
64 32 Kwords
96 Mbits total
Bank A Sectors
Quantity
Size
4 8 Kwords
31 32 Kwords
16 Mbits total
S29NS064J
Bank B, C & D Sectors
Quantity
Size
32 32 Kwords
48 Mbits total
2
S29NS-J
S29NS-J_00_A10 March 22, 2006

6 Page



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部品番号部品説明メーカ
S29NS016J

Burst Mode Flash Memories

SPANSION
SPANSION


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