PDF VSC7135 Data sheet ( Hoja de datos )

Número de pieza	VSC7135
Descripción	Ethernet Transceiver
Fabricantes	Vitesse Semiconductor
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No Preview Available ! www.DataSheet4U.com Data Sheet VSC7135 VITESSE SEMICONDUCTOR CORPORATION 1.25Gbits/sec Gigabit Ethernet Transceiver Features • Gigabit Ethernet Transceiver @ 1.25Gb/s • Compliant to IEEE 802.3Z PMA • TTL Interface Compatible to PMA-TBI • Monolithic Clock Synthesis and Clock Recovery - No External Components • 125MHz TTL Reference Clock • Low Power Operation - 700 mW • Suitable for Both Coaxial or Optical Link Applications • 64 Pin, 14mm or 10mm Standard PQFP • Single +3.3V Supply General Description The VSC7135 is a 1.25Gb/s Ethernet Transceiver optimized for Gigabit Ethernet or 1000Base-X applica- tions. It accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK and serializes it onto the TX PECL differential outputs at a baud rate which is ten times the REFCLK frequency. The VSC7135 also samples serial receive data on the RX PECL differential inputs, recovers the clock and data, deserializes it onto the 10-bit receive data bus, outputs two recovered clocks at one-twentieth of the incoming baud rate and detects “Comma” characters. The VSC7135 contains on-chip PLL circuitry for synthesis of the baud-rate trans- mit clock, and extraction of the clock from the received serial stream. These circuits are fully monolithic and require no external components. VSC7135 Block Diagram EWRAP R0:9 RCLK RCLKN COM_DET EN_CDET T0:9 10 QD Serial to Parallel ÷ 10 ÷ 20 Resync Frame Logic Comma Detect Retimed Data QD Recovered Clock Clock Recovery 2:1 10 DQ Parallel to Serial Serial Data Synthesized Clock DQ RX+ RX- TX+ TX- REFCLK PLL Clock Multiply G52146-0, Rev. 4.0 5/28/98 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 1 1 page VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7135 1.25Gbits/sec Gigabit Ethernet Transceiver AC Characteristics Figure 4: Transmit Timing Waveforms REFCLK T1 T2 T0:9 10 Bit Data Data Valid Data Valid Data Valid Table 1: Transmit AC Characteristics Parameters T1 T2 TSDR,TSDF TLAT TJ TDJ Description Min Max Units T0:9 Setup time to the rising edge of REFCLK T0:9 hold time after the rising edge of REFCLK 1.5 1.0 — ns. — ns. TX+/TX- rise and fall time — 300 ps. Latentcy from rising edge of REFCLK to T0 appearing on TX+/TX- 11bc - 1ns ns. Transmitter Output Jitter Allocation Total data output jitter (p-p) — 192 ps. Serial data output deterministic jitter (p-p) — 80 ps. Conditions Measured between thevalid data level of T0:9 to the 1.4V point of REFCLK 20% to 80%, 75 Ohm load to Vss, Tested on a sample basis bc = Bit clocks ns = Nano second IEEE 802.3Z Clause 38.68, tested on a sample basis IEEE 802.3Z Clause 38.69, tested on a sample basis G52146-0, Rev. 4.0 5/28/98 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 5 5 Page VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7135 1.25Gbits/sec Gigabit Ethernet Transceiver Package Pin Descriptions Figure 9: Pin Diagram VSSD T0 T1 T2 VDDD T3 T4 T5 T6 VDDD T7 T8 T9 VSSD VSSD N/C 63 61 59 57 55 53 51 49 1 47 3 45 5 43 7 41 9 39 11 37 13 35 15 17 19 21 23 25 27 29 31 33 N/C COMDET VSST R0 R1 R2 VDDT R3 R4 R5 R6 VDDT R7 R8 R9 VSST (Top View) Table 4: Pin Identiﬁcation Pin # 2-4, 6-9, 11-13 22 62, 61 45-43, 41- 38, 36-34 Name T0:9 REFCLK TX+, TX- R0:9 Description INPUTS - TTL 10-bit transmit character. Parallel data on this bus is clocked in on the rising edge of REFCLK. The data bit corresponding to T0 is transmitted ﬁrst. INPUT - TTL This rising edge of this clock latches T0:9 into the input register. It also provides the reference clock, at one tenth the baud rate to the PLL. OUTPUTS - Differential PECL (AC Coupling recommended) These pins output the serialized transmit data when EWRAP is LOW. When EWRAP is HIGH, TX+ is HIGH and TX- is LOW. OUTPUTS - TTL 10-bit received character. Parallel data on this bus is clocked out on the rising edges of RCLK and RCLKN. R0 is the ﬁrst bit received on RX+/RX-. G52146-0, Rev. 4.0 5/28/98 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 11 11 Page

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