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PDF S25FL001D Data sheet ( Hoja de datos )
| Número de pieza | S25FL001D | |
| Descripción | (S25FL001D / S25FL002D) Flash Memory | |
| Fabricantes | SPANSION | |
| Logotipo |  |
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S25FL Family (Serial Peripheral Interface)
S25FL002D, S25FL001D
2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory
with 25 MHz SPI Bus Interface
Distinctive Characteristics
PRELIMINARY
INFORMATION
ARCHITECTURAL ADVANTAGES
Single power supply operation
— Full voltage range: 2.7 to 3.6 V read and program
operations
Memory Architecture
— 2 Mb – Four sectors with 512 Kb each
— 1 Mb – Four sectors with 256 Kb each
Program
— Page Program (up to 256 bytes) in 6 ms (typical)
— Program cycles are on a page by page basis
Erase
— 0.25 s typical sector erase time (S25FL001D)
— 0.5 s typical sector erase time (S25FL002D)
— 1.0 s typical bulk erase time (S25FL001D)
— 2.0 s typical bulk erase time (S25FL002D)
Endurance
— 100,000 cycles per sector typical
Data Retention
— 20 years typical
Device ID
— Electronic signature
Process Technology
— Manufactured on 0.25 µm process technology
Package Option
— Industry Standard Pinouts
— 150 mil 8-pin SO package for 1Mb and 2Mb
— 208 mil 8-pin SO package for 2Mb only
— 8-contact WSON leadless package (6x5 mm)
PERFORMANCE CHARACTERISTICS
Speed
— 25 MHz clock rate (maximum)
Power Saving Standby Mode
— Standby Mode 1 µA (typical)
Memory Protection Features
Memory Protection
— W# pin works in conjunction with Status Register Bits
to protect specified memory areas
— Status Register Block Protection bits (BP1, BP0) in
status register configure parts of memory as read-
only
SOFTWARE FEATURES
SPI Bus Compatible Serial Interface
Publication Number 30167 Revision A Amendment +1 Issue Date June 9, 2004
1 page  
Preliminary Information
Connection Diagrams
8-pin Plastic Small Outline Package (SO)
8-contact WSON Package
CS# 1
SO 2
8 VCC
7 HOLD#
CS#
SO
1
2
W#
GND
3
4
6 SCK
5 SI
W#
GND
3
4
Note:
1. 8-pin Plastic Small Outline Package (208 mils) offered for 2Mb density only.
Input/Output Descriptions
SCK
SI
SO
CS#
W#
HOLD#
VCC
GND
=
=
=
=
=
=
=
=
Logic Symbol
Serial Clock Input
Serial Data Input
Serial Data Output
Chip Select Input
Write Protect Input
Hold Input
Supply Voltage Input
Ground Input
VCC
8 VCC
7 HOLD#
6 SCK
5 SI
SI
SCK
CS#
W#
HOLD#
SO
GND
June 9, 2004 30167A+1
S25FL Family (Serial Peripheral Interface)
5
5 Page 
Preliminary Information
To enter the Hold condition, the device must be selected, with Chip Select (CS#)
Low. The Hold condition starts on the falling edge of the Hold (HOLD#) signal,
provided that this coincides with Serial Clock (SCK) being Low (as shown in Figure
3).
The Hold condition ends on the rising edge of the Hold (HOLD#) signal, provided
that this coincides with Serial Clock (SCK) being Low.
If the falling edge does not coincide with Serial Clock (SCK) being Low, the Hold
condition starts after Serial Clock (SCK) next goes Low. Similarly, if the rising
edge does not coincide with Serial Clock (SCK) being Low, the Hold condition ends
after Serial Clock (SCK) next goes Low (Figure 3). During the Hold condition, the
Serial Data Output (SO) is high impedance, and Serial Data Input (SI) and Serial
Clock (SCK) are Don’t Care.
Normally, the device remains selected, with Chip Select (CS#) driven Low, for the
entire duration of the Hold condition. This ensures that the state of the internal
logic remains unchanged from the moment of entering the Hold condition.
Note: Driving Chip Select (CS#) high while HOLD# is still low is not a
valid operation.
SCK
HOLD#
Hold
Condition
(standard use)
Hold
Condition
(non-standard use)
Figure 3. Hold Condition Activation
June 9, 2004 30167A+1
S25FL Family (Serial Peripheral Interface)
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet S25FL001D.PDF ] | |
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