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ADV7391 の電気的特性と機能

ADV7391のメーカーはAnalog Devicesです、この部品の機能は「(ADV7390 - ADV7393) Low Power 10-Bit SD/HD Video Encoder」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADV7391
部品説明 (ADV7390 - ADV7393) Low Power 10-Bit SD/HD Video Encoder
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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ADV7391 Datasheet, ADV7391 PDF,ピン配置, 機能
Data Sheet
Low Power, Chip Scale,
10-Bit SD/HD Video Encoder
ADV7390/ADV7391/ADV7392/ADV7393
FEATURES
3 high quality, 10-bit video DACs
16× (216 MHz) DAC oversampling for SD
8× (216 MHz) DAC oversampling for ED
4× (297 MHz) DAC oversampling for HD
37 mA maximum DAC output current
Multiformat video input support
4:2:2 YCrCb (SD, ED, and HD)
4:4:4 RGB (SD)
Multiformat video output support
Composite (CVBS) and S-Video (Y-C)
Component YPrPb (SD, ED, and HD)
Component RGB (SD, ED, and HD)
Lead frame chip scale package (LFCSP) options
32-lead, 5 mm × 5 mm LFCSP
40-lead, 6 mm × 6 mm LFCSP
Wafer level chip scale package (WLCSP) option
30-ball, 5 × 6 WLCSP with single DAC output
Advanced power management
Patented content-dependent low power DAC operation
Automatic cable detection and DAC power-down
Individual DAC on/off control
Sleep mode with minimal power consumption
74.25 MHz 8-/10-/16-bit high definition input support
Compliant with SMPTE 274M (1080i), 296M (720p),
and 240M (1035i)
EIA/CEA-861B compliance support
NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support
NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz)
Macrovision Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant
Copy generation management system (CGMS)
Closed captioning and wide screen signaling (WSS)
Integrated subcarrier locking to external video source
Complete on-chip video timing generator
On-chip test pattern generation
Programmable features
Luma and chroma filter responses
Vertical blanking interval (VBI)
Subcarrier frequency (fSC) and phase
Luma delay
High definition (HD) programmable features
(720p/1080i/1035i)
4× oversampling (297 MHz)
Internal test pattern generator
Color and black bar, hatch, flat field/frame
Fully programmable YCrCb to RGB matrix
Gamma correction
Programmable adaptive filter control
Programmable sharpness filter control
CGMS (720p/1080i) and CGMS Type B (720p/1080i)
Dual data rate (DDR) input support
Enhanced definition (ED) programmable features
(525p/625p)
8× oversampling (216 MHz output)
Internal test pattern generator
Black bar, hatch, flat field/frame
Individual Y and PrPb output delay
Gamma correction
Programmable adaptive filter control
Fully programmable YCrCb to RGB matrix
Undershoot limiter
Macrovision Rev 1.2 (525p/625p) (ADV7390/ADV7392 only)
CGMS (525p/625p) and CGMS Type B (525p)
Dual data rate (DDR) input support
Standard definition (SD) programmable features
16× oversampling (216 MHz)
Internal test pattern generator
Color and black bar
Controlled edge rates for start and end of active video
Individual Y and PrPb output delay
Undershoot limiter
Gamma correction
Digital noise reduction (DNR)
Multiple chroma and luma filters
Luma-SSAF filter with programmable gain/attenuation
PrPb SSAF
Separate pedestal control on component and
composite/S-Video output
VCR FF/RW sync mode
Macrovision Rev 7.1.L1 (ADV7390/ADV7392 only)
Copy generation management system (CGMS)
Wide screen signaling (WSS)
Closed captioning
Serial MPU interface with I2C compatibility
2.7 V or 3.3 V analog operation
1.8 V digital operation
1.8 V or 3.3 V I/O operation
Temperature range: −40°C to +85°C
W Grade automotive range: −40°C to +105°C
Qualified for automotive applications
Rev. I
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2006–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

1 Page





ADV7391 pdf, ピン配列
Data Sheet
ADV7390/ADV7391/ADV7392/ADV7393
HD CGMS....................................................................................74 
CGMS CRC Functionality .........................................................74 
SD Wide Screen Signaling..............................................................77 
SD Closed Captioning ....................................................................78 
Internal Test Pattern Generation...................................................79 
SD Test Patterns...........................................................................79 
ED/HD Test Patterns ..................................................................79 
SD Timing ........................................................................................80 
HD Timing.......................................................................................85 
Video Output Levels .......................................................................86 
SD YPrPb Output Levels—SMPTE/EBU N10 ........................86 
ED/HD YPrPb Output Levels ...................................................87 
SD/ED/HD RGB Output Levels................................................88 
SD Output Plots ..........................................................................89 
Video Standards ..............................................................................90 
Configuration Scripts .....................................................................92 
Standard Definition ....................................................................92 
Enhanced Definition ..................................................................99 
High Definition .........................................................................101 
ADV7390/ADV7391/ADV7392/ADV7393 Evaluation Board....104 
Outline Dimensions......................................................................105 
Ordering Guide .........................................................................107 
Automotive Products................................................................107 
REVISION HISTORY
2/15—Rev. H to Rev. I
Changed ADV739x to ADV7390/ADV7391/ADV7392/
ADV7393............................................................................. Universal
Changes to Figure 19 ......................................................................19
Changes to Table 15 ........................................................................20
Changes to Figure 144 ..................................................................104
Updated Outline Dimensions......................................................106
Changes to Ordering Guide.........................................................107
9/14—Rev. G to Rev. H
Changed Storage Temperature Range from −60°C to +100°C to
−60°C to +150°C; Table 13.............................................................18
Updated Figure 145, Outline Dimensions .................................105
Changes to Ordering Guide.........................................................107
Deleted ED/HD Nonstandard Timing Mode Section, Figure 63,
and Table 41, Renumbered Sequentially......................................51
Changed SD Subcarrier Frequency Lock, Subcarrier Phase
Reset, and Timing Reset Section to SD Subcarrier Frequency
Lock Section.....................................................................................52
Deleted Subaddress 0x84, Bits[2:1] Section, Timing Reset (TR)
Mode Section, Subcarrier Phase Reset (SCR) Mode Section,
Figure 64, and Figure 65.................................................................52
Changes to Ordering Guide.........................................................121
11/11—Rev. C to Rev. D
Changes to Features Section ............................................................1
Updated Outline Dimensions and changes to Automotive
Products Section............................................................................107
2/13—Rev. F to Rev. G
Change to Features Section..............................................................1
Changes to Table 14 ........................................................................18
Changes to Figure 62 ......................................................................48
Changes to Ordering Guide.........................................................107
11/12—Rev. E to Rev. F
Updated Outline Dimensions......................................................105
Changes to Ordering Guide.........................................................107
2/12—Rev. D to Rev. E
Changes to Table 1 ............................................................................5
Changes to Digital Input/Output Specifications—
1.8 V Section ......................................................................................8
Changes to Table 15 ........................................................................21
Changes to Table 20 ........................................................................31
Changes to Table 23 ........................................................................34
Changes to Table 28 ........................................................................39
Changes to 16-Bit 4:4:4 RGB Mode Section ................................47
Added External Sync Polarity Section..........................................51
9/11—Rev. B to Rev. C
Changes to MPU Port Description Section.................................26
Changes to Ordering Guide.........................................................107
7/10—Rev. A to Rev. B
Changes to Features Section ............................................................1
Change to Applications Section ......................................................5
Changes to General Description .....................................................5
Added Table 2, Renumbered Subsequent Tables ..........................5
Added Figure 2, Renumbered Subsequent Figures ......................6
Changes to Full-Drive Output Current Parameter, Table 5 ........7
Changes to Table 14 ........................................................................18
Added Figure 20 ..............................................................................19
Changes to Table 15 ........................................................................19
Changes to ADV7390/ADV7391 Input Configuration
Section ..............................................................................................45
Added Additional Layout Considerations for the WLCSP
Package Section ...............................................................................71
Added Figure 97 ..............................................................................73
Changes to Configuration Scripts Section...................................92
Changes to Subaddress 0x00, Table 66 .........................................93
Rev. I | Page 3 of 107


3Pages


ADV7391 電子部品, 半導体
ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
GND_IO
VDD_IO
8-BIT SD
OR
8-BIT ED/HD
DGND (2)
FUNCTIONAL BLOCK DIAGRAMS
VDD (2)
SCL SDA ALSB
SFL
AGND VAA
VBI DATA SERVICE
INSERTION
SDR/DDR
SD/ED/HD INPUT
4:2:2 TO 4:4:4
DEINTERLEAVE
ASYNC
BYPASS
YCrCb
HDTV
TEST
PATTERN
GENERATOR
MPU PORT
SUBCARRIER FREQUENCY
LOCK (SFL)
ADV7390/ADV7391
11-BIT
DAC 1
ADD
SYNC
PROGRAMMABLE
LUMINANCE
FILTER
YCrCb
TO
RGB
16×
FILTER
11-BIT
DAC 2
ADD
BURST
PROGRAMMABLE
CHROMINANCE
FILTER
SIN/COS DDS
BLOCK
16×
FILTER
11-BIT
DAC 3
PROGRAMMABLE
ED/HD FILTERS
SHARPNESS AND
ADAPTIVE FILTER
CONTROL
YCbCr
TO
RGB MATRIX
FILTER
POWER
MANAGEMENT
CONTROL
VIDEO TIMING GENERATOR
16×/4× OVERSAMPLING PLL
REFERENCE
AND CABLE
DETECT
DAC 1
DAC 2
DAC 3
RSET
RESET
HSYNC
VSYNC
CLKIN PVDD PGND EXT_LF
Figure 1. ADV7390/ADV7391 (32-Lead LFCSP)
COMP
GND_IO
VDD_IO
8-BIT SD
DGND (2)
VDD (2)
SCL SDA ALSB
SFL
AGND VAA
VBI DATA SERVICE
INSERTION
SDR/DDR
SD INPUT
4:2:2 TO 4:4:4
DEINTERLEAVE
MPU PORT
SUBCARRIER FREQUENCY
LOCK (SFL)
ADV7390BCBZ
ADD
SYNC
PROGRAMMABLE
LUMINANCE
FILTER
16×
FILTER
11-BIT
DAC 1
ADD
BURST
PROGRAMMABLE
CHROMINANCE
FILTER
SIN/COS DDS
BLOCK
16×
FILTER
DAC 1
POWER
MANAGEMENT
CONTROL
VIDEO TIMING GENERATOR
16× OVERSAMPLING PLL
REFERENCE
AND CABLE
DETECT
RSET
RESET
HSYNC
VSYNC
CLKIN PVDD PGND EXT_LF
Figure 2. ADV7390BCBZ-A (30-Ball WLCSP)
COMP
GND_IO
VDD_IO
8-/10-/16-BIT SD
OR
8-/10-/16-BIT ED/HD
DGND (2)
VDD (2)
VBI DATA SERVICE
INSERTION
SDR/DDR
SD/ED/HD INPUT
4:2:2 TO 4:4:4
DEINTERLEAVE
RGB
TO
YCrCb
MATRIX
ASYNC
BYPASS
YCrCb
HDTV
TEST
PATTERN
GENERATOR
SCL SDA ALSB
SFL
AGND VAA
MPU PORT
SUBCARRIER FREQUENCY
LOCK (SFL)
ADV7392/ADV7393
12-BIT
DAC 1
ADD
SYNC
PROGRAMMABLE
LUMINANCE
FILTER
YCrCb
TO
RGB
16×
FILTER
12-BIT
DAC 2
ADD
BURST
PROGRAMMABLE
CHROMINANCE
FILTER
SIN/COS DDS
BLOCK
16×
FILTER
12-BIT
DAC 3
PROGRAMMABLE
ED/HD FILTERS
SHARPNESS AND
ADAPTIVE FILTER
CONTROL
YCbCr
TO
RGB MATRIX
FILTER
POWER
MANAGEMENT
CONTROL
VIDEO TIMING GENERATOR
16x/4x OVERSAMPLING PLL
REFERENCE
AND CABLE
DETECT
DAC 1
DAC 2
DAC 3
RSET
RESET
HSYNC
VSYNC
CLKIN PVDD PGND EXT_LF
Figure 3. ADV7392/ADV7393 (40-Lead LFCSP)
COMP
Rev. I | Page 6 of 107

6 Page



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共有リンク

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部品番号部品説明メーカ
ADV7390

(ADV7390 - ADV7393) Low Power 10-Bit SD/HD Video Encoder

Analog Devices
Analog Devices
ADV7391

(ADV7390 - ADV7393) Low Power 10-Bit SD/HD Video Encoder

Analog Devices
Analog Devices
ADV7392

(ADV7390 - ADV7393) Low Power 10-Bit SD/HD Video Encoder

Analog Devices
Analog Devices
ADV7393

(ADV7390 - ADV7393) Low Power 10-Bit SD/HD Video Encoder

Analog Devices
Analog Devices


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