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PDF STE12PS Data sheet ( Hoja de datos )
| Número de pieza | STE12PS | |
| Descripción | 12-Channel Integrated PSE Line Manager | |
| Fabricantes | Silicon Tech | |
| Logotipo |  |
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STE12PS
12 channel integrated PSE line manager
Preliminary Data
Features
■ PSE power control device
■ Supports up to 12 independent or four 30W,
“boosted” ports
■ Wide operating range: up to 90V
■ IEEE 802.3af compliant
■ Open circuit detection: AC and DC methods
■ Advanced power management algorithm
■ Current sensing with as low as 500mΩ,
external, series resistors
■ No need for external FETs
■ In-rush current control
■ Short-circuit protection
■ Adaptable signature detection capability
■ On-chip 3.3V SMPS controller
■ Low-noise, 12-bit ADC
■ Standard I2C interface
■ Parallel monitor interface
Description
STE12PS is designed to supply power over
multiple Ethernet channels in order to avoid
different, individual power supply units for
applications such as Web cams, IP Phones,
Bluetooth access points and WLAN access
points.
The equipment that provides the power to the
twisted pair cabling is referred to as Power
Sourcing Equipment (PSE).
The PSE’s main functions are: looking for links to
a Powered Device (PD), classifying a PD,
supplying power to the link, monitoring power on
the link, and removing power from the link.
PBGA23x23
The STE12PS is fully programmable, supporting
the detection and powering of IEEE802.3af as
well as legacy PDs. The flexibility of the STE12PS
allows the user to select a suitable system
configuration: up to 12 ports as well as 4
“boosted” channels. If needed, the STE12PS can
also efficiently manage cases or applications
where a limited amount of power is available to
the ports (smart-power capability) by means of
integrated, power MOSFET devices. All
operations are controlled via the I2C bus also
notifying externally some ports status condition
via dedicated pins.
Ethernet port isolation can be easily maintained
thanks to an integrated 3.3V SMPS power source
and by means of optocouplers.
The STE12PS has five address selection inputs
to choose up to 32 possible different addresses.
Power can be provided to the PD using either
spare lines of the Ethernet cable or using the data
wires, as specified by IEEE 802.3af.
November 2006
Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
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STE12PS
Pin description
2 Pin description
Table 1. Analog pins description
Pin name
I/O
Function
IDET_HVLV
O
Anti-aliasing filter capacitor to be connected between the analog input and
ground to improve ADC noise performance. C = 180pF.
IMON_HVLV
O
Anti-aliasing filter capacitor to be connected between the analog input and
ground. C = 180pF.
Vbat_mon
O
Anti-aliasing filter capacitor to be connected between the analog input and
ground. C = 100nF.
Vbatref
O
Anti-aliasing filter capacitor to be connected between the analog input and
ground. C = 100nF.
I_REF
O
Anti-aliasing filter capacitor to be connected between the analog input and
ground. C = 180pF.
CDETSLOW
O Detection rise/fall time capacitor (up to 25nF). Tr/f can be set from 1ns to 4ms.
RSENSE
O SMPS precision, external, current limiting reference resistor: 100mΩ
VDRIVE
O
External p-channel MOSFET gate driving voltage for SMPS. It provides a
square wave with VL as upper limit and (VL-10V) as lower limit voltage.
SFTSTR
O Switched Mode Power Supply (SMPS) soft start capacitor, 200nF.
FB IO SMPS feedback pin, Cfb = 2.2nF
Pn
O
Power DMOS device drain, if DMOS is turned-on, channel “n” where n = 1,…12
is activated.
ACSn
O It provides a 50Hz AC disconnection signal for port “n”, n = 1, … 12.
SPn I Detection classification and AC disconnection sensing port “n”, n = 1, … 12.
SSRPn
Line current to the monitoring resistor for channel “n”, n = 1,… 12. Allowed
I values are 0.523, 1.05, 1.58 and 2.1ohms (see also SENSPROG preset pins).
Sensing pin.
FSRPn
O
Source terminal for power DMOS connected to the sense resistor for channel
“n”, n = 1,… 12, a “forcing” pin.
RMONF
RMONS
RREF
O
Mirror monitoring resistance (500 × Rsense) pin to let internal ADC evaluate line
currents. Forcing pin.
O
Mirror monitoring resistance (500 × Rsense) pin to let internal ADC evaluate line
currents. A “sensing” pin.
I Reference bias resistor: 18.7kΩ
CLK_GEN1
I Crystal oscillator pin1 for high performance clock generation.
CLK_GEN2
I Crystal oscillator pin2 for high performance clock generation.
MCLK
O Master clock output for multi device configuration.
CLK_GEN3
I Low profile clock input pin or clock input pin in multi-device configuration.
ACin
I 50Hz sinusoidal input
ACout
O 50Hz sinusoidal output, internally generated
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STE12PS
Functional description
By default, the STE12PS will recognize a valid signature with the following characteristics:
– an inverse slope of the port current vs. voltage (I-V) characteristic measuring
between 19 and 26.5kΩ (Rdl and Rdh),
– a port capacitance of less than 4µF.
If required, the STE12PS can also perform a custom, resistive detection search – modifying
the acceptance window. This can be easily performed by changing the Rdh and Rdl limits or
by changing Gdl and Gdh via the logic interface.
In Midspan applications, where power is applied via spare wires, when the PSE fails to
detect a PD, the port remains in high-impedance (Hi-Z) for at least two seconds. If the
signature resistance is greater than 500kΩ, then the two second wait is avoided.
Transition rates of the port voltage between the two probing levels can be adjusted with
capacitance Cdetslow.
Table 4. PD power classification
Class Usage
Maximum power level at
PSE output (Pall)
0 Default 15.4W (programmable)
1 Optional
4W (programmable)
2 Optional
7W (programmable)
3 Optional 15.4W (programmable)
4 Optional
-
0 Default 15.4W (programmable)
Power level at PD input
0.44 to 12.95W
0.44 to 3.84W
3.84 to 6.49W
6.49 to 12.95W
Reserved
0.44 to 12.95W
Iclass
Iclass < Ithcl0
Ithcl0 < Iclass < Ithcl1
Ithcl1< Iclass < Ithcl2
Ithcl2 < Iclass < Ithcl3
Ithcl3 < Iclass < Ithcl4
Ithcl4 < Iclass
3.2.2
Note:
Classification
Once a valid signature is detected, the port is probed for classification in order to perform
smart-power management (if enabled).
Port probing is performed by forcing a DC voltage in the range of 16V to 18V (one DC
generator multiplexed between the channels) and monitoring current Iclass. The
measurement is repeated and stored in the Channel Monitor Classification registers to
ensure a coherent classification. The PD power class is defined as shown in Table 4 above.
The detected class is then stored in the Channel Status registers.
The power absorbed in a link is calculated considering the actual value of the battery
voltage in order to arrive at a true power measurement result.
11/44
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