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PDF STE101P Data sheet ( Hoja de datos )
| Número de pieza | STE101P | |
| Descripción | 10/100 Fast Ethernet 3.3V Transceiver | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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STE101P
10/100 Fast ethernet 3.3 V transceiver
Features
■ IEEE802.3u 100Base-TX and IEEE802.3 and
10Base-T transceiver
■ Support for IEEE802.3x flow control
■ MII /RMII / SMII interface
■ Auto MDIX supported
■ Provides Full-duplex operation on both
100Mbps and 10Mbps modes
■ Provides MLT-3 transceiver with DC
restoration for Base-line wander compensation
■ Provides loop-back modes for diagnostics
■ Supports external transformer with turn ratio
1.414:1 on Tx/Rx side.
■ Five LED display for operating mode and
functionality signalling
■ Operation from single 3.3V supply
■ High Cable ESD tolerance
■ Standard 64-pin QFP package pinout
■ Industrial temperature compliant
■ Self termination transceiver for external
components and power saving
■ Power dissipation < 200mW
Applications
■ Switches/routers/hubs
■ NIC adapters
■ Game consoles
■ VoIP gateways/phones
■ Network printers
■ DTVs/DVD-Rs
TQFP64 10 x 10
Description
The STE101P is a high performance Fast
Ethernet physical layer interface for 10Base-T and
100Base-TX application.
It was designed with advanced CMOS technology
to provide MII, RMII and SMII interfaces for easy
attachment to 10/100 Media Access Controllers
100Base-TX of IEEE802.3u and 10Base-T of
IEEE802.3
The STE101P supports both half-duplex and full-
duplex operation at 10 and 100 Mbps operation.
Its operating mode can be set using auto
negotiation, parallel detection or manual control. It
also allows for the support of auto-negotiation
functions for speed and duplex detection. The
Automatic MDI / MDIX feature compensates for
using a cross over cable. With Auto MDIX, the
STE101P automatically detects what is on the
other end of the network cable and switches the
TX & RX pins accordingly.
September 2006
DataSheet4 U .com
Rev 1
1/53
www.st.com
1
1 page  
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STE101P
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
System diagram of the STE101P application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
LED connection for Logic level 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
LED connection for Logic level 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Transmit isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Normal link pulse timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Fast link pulse timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
MII management clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
MII receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
MII transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
RMII transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
RMII receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
SMII transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SMII receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
TQFP 64 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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STE101P
Pin description
Table 1. Pin description (continued)
Pin No. Name
Type
Description
64 cfg0
Configuration Control 0.
When A/N is enabled, cfg0 determines operating mode advertisement
capabilities in combination with cfg1 when mf0/ PR00:12 =1. (See Table 2)
I When A/N is disabled, cfg1 disables mlt3 and directly affects PR13:0
When cfg0 is Low, mlt3 encoder/decoder is enabled and PR13:1 =0.
When cfg0 is High, mlt3 encoder/decoder is bypassed and PR13:1 = 1.
63 cfg1
Configuration Control 1.
When A/N is enabled, cfg1 determines operating mode advertisement
capabilities in combination with cfg1 when mf0/ PR00:12 =1. (See Table 2)
I When A/N is disabled, CFG1 enables Loopback mode and directly affects
PR00 bit 14.
When cfg1 is Low, Loopback mode is disabled and PR00:14 = 0.
When cfg1 is High, Loopback mode is enabled and PR00:14 = 1.
28 reset
Reset (Active-Low). This input must be held low for a minimum of 1 ms to reset
I the STE101P. During Power-up, the STE101P will be reset regardless of the
state of this pin. Reset will not be complete until >1ms plus an MDC transition.
29 rip
Reset In Progress. This output is used to indicate when the device has
completed power-up/reset and the registers and functions can be accessed.
O When rip is High, power-up/reset has been successful and the device can be
used normally
When rip is Low, device reset is not complete.
30 mdix_dis
Auto MDI/MDIX disable
31 cf2
32 sclk
NC for MII operation. Should be tied high for RMII/SMII operation. See Table 2.
NC for MII operation. System clock for RMII (50MHz) and SMII (125MHz)
26, 33
test,
test_se
27 pwrdwn
Test pins. Should be tied to ground for normal operation
Power Down. When High, forces STE101P into Power Down mode. This pin is
I
OR’ed with the Power Down bit (PR00:11). During the Power Down mode,
txp/txn outputs and all LED outputs are 3-stated, and the MII interface is
isolated.
Multi-function pins. Each mf pin internally drives different configuration
functions. The functions of the five mf inputs are as shown in the table below.
5 mf0
4 mf1
3 mf2
2 mf3
1 mf4
I
Pin Function
mfo Auto negotiation
mf1 Enable NRZ, NRZI conversion
mf2 4B/5B coding enable
mf3 Scrambler operation disable
mf4 10/100Mbps speed select
Reg. & Bit affected
PR00:12
PR13:7
PR13:6
PR13:0
PR00:13
The logic level of mf0-4 will determine the value that the affected bits will have
upon reset of the STE101P. The operating functions of cfg0, cfg1, and fde
change depending on the state of mf0 (Auto-Negotiation enabled or disabled).
Table shows the relationship between cfg0, cfg1 and fde.
11/53
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