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PDF VSP9402A Data sheet ( Hoja de datos )
| Número de pieza | VSP9402A | |
| Descripción | (VSP94x2A) TV/Video IC | |
| Fabricantes | Micronas Semiconductor | |
| Logotipo |  |
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MICRONAS
PRELIMINARY DATA SHEET
VSP 94x2A
PRIMUS
Powerful Scan-Rate
Converter including
Multistandard
Color Decoder
Edition Aug. 28, 2002
6251-552-4PD
DataSheet4 U .com
MICRONAS
1 page  
www.DataSheet4U.com
PRELIMINARY DATA SHEET
VSP 94x2A
1.1. Features
– Integrated Video Matrix switch
• Up to seven CVBS inputs, up to two Y/C inputs,
• Three CVBS outputs (Y/C inputs signals are com-
bined to CVBS output format)
• 9 bit amplitude resolution for CVBS, Y/C A/D con-
verter
• AGC (Automatic Gain Control)
– Multi-standard color decoder
• PAL/NTSC/SECAM including all substandards
• Automatic recognition of chroma standard
• Only one crystal necessary for all standards
– RGB-FBL or YUV-H-V input
• 8 bit amplitude resolution for RGB or YUV
• 8 bit amplitude resolution for FBL or H
– ITU656 support (version dependent, refer to next
chapter)
• ITU656 input/output
• DS656 output (double-scan ’656-like’ output)
– Letterbox detection
– Noise reduction
• Temporal noise reduction
• Field-based temporal noise reduction for lumi-
nance and chrominance
• Different motion detectors for luminance and
chrominance or identical
• Flexible programming of the temporal noise
reduction parameters
• Automatic measurement of the noise level
– Horizontal scaling of the 1fH signal
• Split-screen possible with additional PiP or Text
processor
– Flexible digital horizontal scaling of the 2fH signal
• Scaling factors: 3, ..., 0.75 including 16:9 compat-
ibility
• 5 zone panorama generator
– Embedded memory
• On-chip memory controller
• Embedded DRAM core for field memory
• SRAM for PAL/SECAM delay line
– Data format 4:2:2
– Flexible clock and synchronization concept
• Horizontal line-locked or free-running mode
• Vertical locked or free-running mode
– Scan-rate-conversion
• Simple interlaced modes (100/120 Hz): AABB,
AAAA, BBBB (9402A/9412A only)
• No scan-rate-conversion modes (50/60 Hz): AB,
AA, BB (9432A/9442A only)
– Flexible output sync controller
• Flexible positioning of the output signal
• Flexible programming of the output sync raster
• ’Blank signal’ generation
– Signal manipulations
• Still field
• Insertion of colored background
• Windowing
• Vertical chrominance shift for improved VCR pic-
ture quality
– Sharpness improvement
• Digital color transition improvement (DCTI)
• Peaking (luminance)
– Three D/A converters
• 9 bit amplitude resolution for Y, -(R-Y), -(B-Y) out-
put
• 72 MHz clock frequency
• Two-fold oversampling for Anti-imaging
• Simplification of external analog postfiltering
– 1920 active pixel/per line in default configuration
– I2C-bus control (400 kHz)
• selectable I2C address
– 1.8 V ± 5% and 3.3 V ± 5% supply voltages
– MQFP80B package
Micronas
DataSheet4 U .com
Aug. 28, 2002; 6251-552-4PD
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PRELIMINARY DATA SHEET
can be adjusted by DEEMPFIR and DEEMPIIR. The
bell filter can be adjusted by BELLFIR and BELLIIR.
The delay between Y and C is well aligned and can
also be adjusted in steps of 50 ns (YCDEL). No picture
shifting occurs when switching between different color
standards (e.g. SECAM -> PAL). A delay-line is imple-
mented for PAL and SECAM signals. It acts as a sim-
ple chrominance comb-filter for NTSC and can be dis-
abled by COMB. This improves the vertical chroma
resolution, but cross-color remains.
Chroma filter
5
0
5
10
15
20
25
30 CHRF=’001001’
35
CHRF=’111001’
40
0 0.5 1 1.5 2 2.5
Frequency (MHz)
CHRF=’001000’
CHRF=’001100’
CHRF=’001110’
3 3.5
4
Fig. 2–6: Chroma filter characteristics
IF Prefilter
10
3.58 4.433
5
0
IFCOMP=’000’
5
IFCOMP=’011’
10
IFCOMP=’100’
15
IFCOMP=’001’
20
IFCOMP=’010’
25
30
01 23 4
Frequency (MHz)
5
Fig. 2–7: IF prefilter
6
VSP 94x2A
Micronas
DataSheet4 U .com
Aug. 28, 2002; 6251-552-4PD
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet VSP9402A.PDF ] | |
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