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V6150 の電気的特性と機能

V6150のメーカーはETCです、この部品の機能は「Power Surveillance and Software Monitoring」です。


製品の詳細 ( Datasheet PDF )

部品番号 V6150
部品説明 Power Surveillance and Software Monitoring
メーカ ETC
ロゴ ETC ロゴ 




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V6150 Datasheet, V6150 PDF,ピン配置, 機能
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EM MICROELECTRONIC-MARIN SA
V6150
Power Surveillance and Software Monitoring
Features
n Standby mode, maximum current 45 mA
n Reset output guaranteed for VDD voltage
down to 1.2 V
n Comparator for voltage monitoring,
voltage reference 1.5 V
n Programmable reset voltage monitoring
n Programmable power-on reset (POR) delay
n Watchdog with programmable time window
guarantees a minimum time and a maximum time
between software clearing of the watchdog
n Time base accuracy ± 10%
n System enable (EN) output offers added security
n TTL / CMOS compatible
n -40 to +85 °C temperature range
n On request extended temperature range,
40 to +125 °C
n DIP8 and SO8 packages
Description
The V6150 offers a high level of integration by voltage
monitoring and software monitoring in an 8 lead
package. A comparator monitors the voltage applied at
the VIN input comparing it with an internal 1.5 V
reference. The power-on reset function is initialized after
VIN reaches 1.5 V and takes the reset output inactive
after TPOR depending of external resistance. The reset
output goes active low when the VIN voltage is less than
1.5 V. The RES and EN outputs are guaranteed to be in
a correct state for a supply voltage as low as 1.2 V. The
watchdog function monitors software cycle time and
execution. If the software clears the watchdog too
quickly (incorrect cycle time) or too slowly (incorrect
execution), it will cause the system to be reset. The
system enable output prevents critical control functions
being activated until software has successfully cleared
the watchdog three times. Such a security could be
used to prevent motor controls being energized on
repeated resets of a faulty system.
Applications
n Automotive systems
n Cellular telephones
n Security systems
n Battery powered products
n Industrial electronics
Typical Operating Configuration
Version 00:
Version 01:
VDD
V6150
R VIN
TCL
VSS
RES
EN
GND
Pin Assignment
DIP8 / SO8
Fig. 1
EN
RES
TCL
VSS
V6150
VIN
R
VDD
NC
Fig. 2
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V6150 pdf, ピン配列
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V6150
ISS Standby versus Temperature at VDD = 5 V
3480
36
34
3302
28
26
24
22
20
18
16
14
12
10 40 30 20 10
0
10 20 30 40 50 60 70 80
TA [°C]
Fig. 3
Timing Characteristics
VDD = 5.0 V ± 3%, C = 100 nF, TA = 40 to +85 °C, unless otherwise specified
Parameter
Symbol Test Conditions
Propagation delays:
TCL to Output Pins
VIN sensitivity
Logic Transition Times on all Output Pins
Power-on Reset delay
Watchdog Time
Open Window Percentage
Closed Window Time
Open Window Time
Watchdog Reset Pulse
TCL Input Pulse Width
TDIDO
TSEN
TTR
TPOR
TWD
OWP
TCW
TCW
TOW
TOW
TWDR
TWDR
TTCL
Load 10 k, 50 pF
REXT = 123 k, ±1%
REXT = 123 k, ±1%
REXT = 123 k, ±1%
REXT = 123 k, ±1%
REXT = 123 k, ±1%
Timing Waveforms
Watchdog Timeout Period
Min.
Typ.
Max. Units
250 500
1 5 20
30 100
90 100 110
90 100 110
±0.2 TWD
0.8 TWD
72 80 88
0.4 TWD
36 40 44
TWD / 40
2.5
150
ns
µs
ns
ms
ms
ms
ms
ms
ns
Table 4
TWD = TPOR
OWP
20%
+ OWP
+ 20%
Condition:
REXT = 123 k
Watchdog
timer reset
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TCW – closed window
TOW – open window
80 100 120
t [ms]
Fig. 4
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V6150
The open window starts after the closed time window
finishes and lasts till TWD + OWP(TWD). The open window
time is defined by TOW = 2 x OWP(TWD).
For example if TWD = 100 ms (actual value) and OWP =
± 20% this means the closed window lasts during first
the 80 ms (TCW = 80 ms = 100 ms 0.2 (100 ms)) and
the open window the next 40 ms (TOW = 2 x 0.2 (100 ms)
= 40 ms). The watchdog can be serviced between 80
ms and 120 ms after the timer reset. However as the
time base is ± 10% accurate, software must use the
following calculation as the limits for servicing signal
TCL during the open window:
Related to curves (Fig. 10 to Fig. 20), especially Fig. 19
and Fig. 20, the relation between TWD and REXT could
easily be defined. Let us take an example describing the
variations due to production and temperature:
1. Choice, TWD = 26 ms.
2. Related to Fig. 20, the coefficient (TWD to REXT) is 1.155
where REXT is in kW and TWD in ms.
3. REXT (typ.) = 26 x 1.155 = 30.0 kW.
4. 26 ms at +25 °C
a)(26 - 10% = 23.4 ms) (26 + 10% = 28.6 ms)a)
b)(23.4 - 5% = 22.2 ms)
(28.6 + 5% = 30.0 ms)b)
min.: (30.0 - 20% = 24.0 ms) max.: (22.2 + 20% = 26.7 ms)
Typical TCL period of
(24.0 + 26.7) / 2 = 25.4 ms
The ratio between TWD = 26 ms and the (TCL
period)= 25.4 ms is 0.975.
Then the relation over the production and the full
temperature range is, TCL period = 0.975 x
TCL
period
=
0.975 x R
1.155
EXT
,
as
typical
value.
TWD
or
a) While PRODUCTION value unknown for the custo-
mer when REXT ¹ 123 kW.
b) While operating TEMPERATURE range
-40 °C TA +85 °C.
5. If you fixed a TCL period = 26 ms
ÞREXT
26 x 1.155
0.975
= 30.8 kW.
If during your production the TWD time can be measur-
ed at TA = +25 °C and the mC can adjust the TCL
period, then the TCL period range will be much larger
for the full operating temperature.
Timer Clearing and RES Action
The watchdog circuit monitors the activity of the
processor. If the user’s software does not send a pulse
to the TCL input within the programmed open window
timeout period, a short watchdog RES pulse is
generated which is equal to TWD/40 = 2.5 ms typically
(see Fig. 6).
With the open window constraint, new security is added
to conventional watchdogs by monitoring both software
cycle time and execution. Should software clear the
watchdog too quickly (incorrect cycle time) or too slowly
(incorrect execution), it will cause the system to be reset.
If the software is stuck in a loop which includes the
routine to clear the watchdog, then a conventional
watchdog would not make a system even though the
software is malfunctioning; the V6150 would make a
system reset because the watchdog would be cleared
too quickly.
If no TCL pulse is applied before the closed and open
windows expire, RES will start to generate square waves
of period TCW + TOW + TWDR. The watchdog will remain
in this state until the next TCL falling edge appears
during an open window, or until a fresh power-up
sequence. The system enable output, EN, can be used
to prevent critical control functions being activated in the
event of the system going into this failure mode (see
section “Enable - EN Output”).
The RES output must be pulled up to VDD even if the
output is not used by the system (see Fig. 9).
Combined Voltage and Timer Action
The combination of voltage and timer actions is
illustrated by the sequence of events shown in Fig. 7. On
power-up, when the voltage at VIN reaches VREF, the
power-on-reset, POR, delay is initialized and holds RES
active for the time of the POR delay. A TCL pulse will
have no effect until this power-on-reset delay is
completed. After the POR delay has elapsed, RES goes
inactive and the watchdog timer starts acting. If no TCL
pulse occurs, RES goes active low for a short time TWDR
after each closed and open window period. A TCL pulse
coming during the open window clears the watchdog
timer. When the TCL pulse occurs too early (during the
closed window), RES goes active and a new timeout
sequence starts. A voltage drop below the VREF level for
longer than typically 5 ms, overrides the timer and
immediately forces RES active and EN inactive. Any
further TCL pulse has no effect until the next power-up
sequence has completed.
Enable - EN Output
The system enable output, EN, is inactive always when
RES is active and remains inactive after a RES pulse
until the watchdog is serviced correctly 3 consecutive
times (ie. the TCL pulse must come in the open
window). After three consecutive services of the
watchdog with TCL during the open window, the EN
goes active low.
A malfunctioning system would be repeatedly reset by
the watchdog. In a conventional system critical motor
controls could be energized each time reset goes
inactive (time allowed for the system to restart) and in
this way the electrical motors driven by the system could
function out of control. The V6150 prevents the above
failure mode by using the EN output to disable the motor
controls until software has successfully cleared the
watchdog three times (i.e. the system has correctly
restarted after a reset condition).
For the version 00 the EN output must be pulled up to
VDD even if the output is not used by the system (see
Fig.9).
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部品番号部品説明メーカ
V6150

Power Surveillance and Software Monitoring

ETC
ETC
V6155

Extremely Accurate Power Surveillance

EM Microelectronic
EM Microelectronic


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