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Número de pieza | STA320 | |
Descripción | 2.1 MULTICHANNELS DIGITAL AUDIO PROCESSOR WITH DDTM | |
Fabricantes | ST Microelectronics | |
Logotipo | ||
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STA320
2.1 MULTICHANNELS DIGITAL AUDIO
PROCESSOR WITH DDX™
1 FEATURES
■ 2.1 Channels of 24-bit DDXTM
Figure 1. Package
■ >100dB SNR and Dynamic Range
■ Selectable 32kHz-192kHz Input Sample Rates
■ I2C control with Selectable Device Address
■ Digital Gain/Attenuation +48dB to -90dB in
SO28
0.5dB steps
■ Soft Volume Update
■ Individual Channel and Master Gain/
Table 1. Order Code
Part Number
Package
Attenuation
STA320
SO28
■ Dual Independent Limiters/Compressors
■ Dynamic Range Compression or Anti-Clipping
Modes
■ AutoModesTM:
■ Post-EQ User Programmable mix
■ User Programmable 2.1 Bass Management
– 7 Preset Crossover filters
■ Sub Channel Mix into Left and Right Channels
– 32 Preset EQ Settings
■ Advanced AM Interference Frequency
– Auto Volume Controlled Loudness
Switching and Noise Suppression Modes
– 3 Preset Volume Curves
■ Selectable High or Low Bandwidth Noise
– 2 Preset Anti-Clipping Modes
– Preset Nighttime Listening Mode
DataSheet4U.Scohmaping
■ Variable
Topologies
Max Power
Correction
for
lower
full-
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– Preset TV AGC
power THD
■ Individual Channel and Master Soft and Hard
■ 3 or 4 Output Routing Configurations
Mute
■ Selectable Clock Input Ratio
■ Independent Channel Volume and DSP Bypass
■ Automatic Zero-Detect Mute
■ 96kHz Internal Processing Sample Rate, 24 to
28-bit precision
■ Automatic Invalid Input Detect Mute
■ 2-Channel I2S Input Data Interface
2 DESCRIPTION
■ Input and Output Channel Mapping
■ 4 28-bit User Programmable Biquads (EQ) per
channel
■ Bass/Treble Tone Control
The STA320 is a single chip solution for digital audio
processing and control in 2.1-channel applications. It
provides output capabilities for DDXTM (Direct Digital
Amplification). In conjunction with a DDXTM power
■ DC Blocking Selectable High-Pass Filter
device, it provides high-quality, high-efficiency, all
■ Selectable De-emphasis
digital amplification.
DataSheet4U.com
November 2005
This is preliminary information on a new product now in development. Details are subject to change without notice.
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STA320
4.1.3 Stop Condition
STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the
high state.
A STOP condition terminates communication between STA320 and the bus master.
4.1.4 Data Input
During the data input the STA320 samples the SDA signal on the rising edge of clock SCL. For correct device
operation the SDA signal must be stable during the rising edge of the clock and the data can change only when
the SCL line is low.
4.2 DEVICE ADDRESSING
To start communication between the master and the STA320, the master must initiate with a start condition.
Following this, the master sends onto the SDA line 8-bits (MSB first) corresponding to the device select address
and read or write mode.
The 7 most significant bits are the device address identifiers, corresponding to the I2C bus definition. In the
STA320 the I2C interface has two device addresses depending on the SA port configuration, 0x34 when SA =
0, and 0x36 when SA = 1.
The 8th bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0 for write mode and
0 for write mode. After a START condition the STA320 identifies on the bus the device address and if a match
is found, it acknowledges the identification on SDA bus during the 9th bit time. The byte following the device
identification byte is the internal space address.
4.3 WRITE OPERATION
Following the START condition the master sends a device select code with the RW bit set to 0.
et4U.coTmhe STA320 acknowledges this and the writeDs afotar Sthheebeytt4eUo.fcoinmternal address.
After receiving the internal byte address the STA320 again responds with an acknowledgement.
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4.3.1 Byte Write
In the byte write mode the master sends one data byte, this is acknowledged by the STa320. The master then
terminates the transfer by generating a STOP condition.
4.3.2 Multi-byte Write
The multi-byte write modes can start from any internal address. The master generating a STOP condition ter-
minates the transfer.
Figure 3. Write Mode Sequence
BYTE
WRITE
START
MULTIBYTE
WRITE
START
DEV-ADDR
DEV-ADDR
ACK
RW
ACK
RW
SUB-ADDR
ACK
SUB-ADDR
ACK
DATA IN
DATA IN
ACK
STOP
ACK
DATA IN
ACK
STOP
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STA320
5.2.4 Channel Input Mapping
BIT R/W RST
NAME
DESCRIPTION
6 R/W
0
C1IM
0 – Processing channel 1 receives Left I2S Input
1 – Processing channel 1 receives Right I2S Input
7 R/W
1
C2IM
0 – Processing channel 2 receives Left I2S Input
1 – Processing channel 2 receives Right I2S Input
Each channel received via I2S can be mapped to any internal processing channel via the Channel Input
Mapping registers. This allows for flexibility in processing. The default settings of these registers map each
I2S input channel to its corresponding processing channel.
5.3 Configuration Register C(Address 02h)
D7 D6 D5 D4
OCRB
CSZ4
CSZ3
CSZ2
11 0 0
D3
CSZ1
0
D2
CSZ0
0
D1
OM1
1
D0
OM0
0
5.3.1 DDX Power Output Mode
BIT R/W RST
NAME
0 R/W
0
OM0
1 R/W
1
OM1
DESCRIPTION
DDX Power Output Mode: Selects configuration of DDX
output.
The DDX Power Output Mode selects how the DDX output timing is configured. Different power devices use
et4U.codmifferent output modes. The STA50x or STA5D1axtraeSchoememt4eUnd.ceodmuse is OM = 10.
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Table 13. Output Modes
OM(1,0)
00
01
10
11
Output Stage – Mode
STA50x/STA51x – Drop Compensation
Discrete Output Stage – Tapered Compensation
STA50x/STA51x – Full Power Mode
Variable Drop Compensation (CSZx bits)
5.3.2 DDX Compensating Pulse Size Register
BIT R/W RST
NAME
DESCRIPTION
2 R/W
3 R/W
4 R/W
0
0
0
CSZ0
CSZ1
CSZ2
Contra Size Register: When OM(1,0) = 11, this register
determines the size of the DDX compensating pulse from 0
clock ticks to 31 clock periods.
5 R/W
0
CSZ3
6 R/W
1
CSZ4
Table 14. Compensating Pulse Size
CSZ(4..0)
00000
00001
…
11111
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Compensating Pulse Size
0ns(0 tick) Compensating Pulse Size
10ns(1 tick) Clock period Compensating Pulse Size
…
310ns(31 tick) Clock period Compensating Pulse Size
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Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet STA320.PDF ] |
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