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SB61L256BのメーカーはSilicon-Based Technologyです、この部品の機能は「Static CMOS RAM」です。 |
部品番号 | SB61L256B |
| |
部品説明 | Static CMOS RAM | ||
メーカ | Silicon-Based Technology | ||
ロゴ | |||
このページの下部にプレビューとSB61L256Bダウンロード(pdfファイル)リンクがあります。 Total 8 pages
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Silicon-Based Technology
SB61L256B
32,768 x 8-Bits
Ultra High Speed and Low Power Memory
STATIC CMOS RAM
PRELIMINARY
Description:
The SB61L256B series products are 32,768-words by 8-bits static RAMs fabricated with advanced
8" wafer submicron CMOS technology. Using unique CMOS peripheral circuits and special poly-
load 4-transistor memory cells, the SB61L256B series products exhibit very high-speed
performance with single +3.3-volt power supply while requiring very low power and no clock or
refreshing to operate. The SB61L256B is packed in a standard 28-pin 300mil SOJ.
Features:
• 32,768-word x 8-bit organization
• Single +3.3-volt power supply
• Fully static operation no clock or refreshing required
• LVTTL-compatible inputs and outputs
• Common I/O capability
• Low power consumption
Active: 130/120/110 mA(Max.)
Standby: 2 mA
• Very high speed access: 6.5/7/8 ns(Max.)
• 28-pin plastic 300 mil SOJ package
• Output Enable( OE )available for very fast access
Ordering Information:
Part Number
Package
Word
Organization
Access
Time
ns(Max.)
Supply
Voltage
(Typ.)
Supply Current mA
(Max.)
Operating Standby
SB61L256B-6.5
SB61L256B-7
28-Pin Plastic
SOJ
32K× 8 bits
6.5
7
SB61L256B-8
(300 mil)
8
The information in this document is subject to change without notice
3.3V± 5%
130
120
110
2
SBT Silicon-Based Technology Corporation
1F,No.23, R&D Rd.I, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C.
-1-
Tel:886-35-777897
Fax:886-35-779832
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SBT
Block Diagram:
SB61L256B
Preliminary
AAAAAAAAA11793568424
Row
Address
Buffer
9
512
Row
Decoders
Memory Cell
Array
512 Rows
512 Columns
I/O1〜I/O8 •8
Input
Data
Control
•8
Sense/Switch
512
Column
Decoders
8
Output
Data
Control
CS •
•
OE
WE •
•
6
Column Address
Buffer
A13A11A10A2 A1 A0
Truth Table:
CS OE
HX
LH
LL
LX
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WE Mode
I/O1〜I/O8
X Not Selected
High Z
H Output Disable
High Z
H Read
Data Out
L Write
Data In
-3-
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VDD Current
ISB,ISB1
IDD
IDD
IDD
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SBT
SB61L256B
Preliminary
AC Performances:
(VDD = 3.3V ± 5%, VSS = 0V, Ta = 0 to 70℃)
(1) Read Cycle
Parameters
Symbols SB61L256B-6.5
Min. Max.
Read Cycle Time
TRC 6.5 -
Address Access Time
TAA - 6
Chip Select Access Time
TACS
-
6
Output Enable to Output Valid
TAOE
-
4
Chip Selection to Output in Low Z TCLZ*
3
-
Output Enable to Output in Low Z TOLZ*
0
-
Chip Deselection to Output in High Z TCHZ*
-
3
Output Disable to Output in High Z TOHZ*
-
3
Output Hold from Address Change TOH
*These parameters are sampled but not 100% tested
3
-
SB61L256B-7
Min. Max.
7-
-7
-7
- 4.5
3-
0-
- 3.5
- 3.5
3-
SB61L256B-8
Min. Max.
8-
-8
-8
-5
3-
0-
-4
-4
3-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2) Write Cycle
Parameters
Symbols SB61L256B-6.5 SB61L256B-7 SB61L256B-8 Unit
Min. Max. Min. Max. Min. Max.
Write Cycle Time
TWC 6.5 -
7-
8 - ns
Chip Selection to End of Write
TCW
4-
5-
6 - ns
Address Valid to End of Write
Address Setup Time
TAW
TAS
4-
0-
5-
0-
6 - ns
0 - ns
Write Pulse Width
TWP 4 -
5-
6 - ns
Write Recovery Time
TWR
0-
0-
0 - ns
Data Valid to End of Write
TDW
4-
4.5 -
5 - ns
Data Hold from End of Write
TDH 0 -
0-
0 - ns
Write to Output in High Z
TWHZ* -
3
- 3.5 -
4 ns
Output Disable to Output in High Z TOHZ*
Output Active from End of Write
TOW
* These parameters are sampled but not 100% tested
-
0
3
-
- 3.5 -
4 ns
0-
0 - ns
-6-
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ページ | 合計 : 8 ページ | ||
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PDF ダウンロード | [ SB61L256B データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
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SB61L256BT | Static CMOS RAM | Silicon-Based Technology |
SB61L256C | Static CMOS RAM | Silicon-Based Technology |