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P-80C32 の電気的特性と機能

P-80C32のメーカーはTemicです、この部品の機能は「(P-80C32 / P-80C52) CMOS 8-Bit Microcontroller」です。


製品の詳細 ( Datasheet PDF )

部品番号 P-80C32
部品説明 (P-80C32 / P-80C52) CMOS 8-Bit Microcontroller
メーカ Temic
ロゴ Temic ロゴ 




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P-80C32 Datasheet, P-80C32 PDF,ピン配置, 機能
www.DataSheet4U.com
80C32/80C52
CMOS 0 to 44 MHz Single Chip 8–bit Microcontroller
1. Description
TEMIC’s 80C52 and 80C32 are high performance
CMOS versions of the 8052/8032 NMOS single chip 8
bit Microcontroller.
The fully static design of the TEMIC 80C52/80C32
allows to reduce system power consumption by bringing
the clock frequency down to any value, even DC,
without loss of data.
The 80C52 retains all the features of the 8052: 8 K bytes
of ROM; 256 bytes of RAM; 32 I/O lines; three 16 bit
timers; a 6-source, 2-level interrupt structure; a full
duplex serial port; and on-chip oscillator and clock
circuits. In addition, the 80C52 has 2
D 80C32: Romless version of the 80C52
D 80C32/80C52-L16: Low power version
VCC: 2.7 – 5.5 V Freq: 0-16 MHz
D 80C32/80C52-12: 0 to 12 MHz
D 80C32/80C52-16: 0 to 16 MHz
D 80C32/80C52-20: 0 to 20 MHz
D 80C32/80C52-25: 0 to 25 MHz
D 80C32/80C52-30: 0 to 30 MHz
D 80C32/80C52-36: 0 to 36 MHz
software-selectable modes of reduced activity for
further reduction in power consumption. In the idle
mode the CPU is frozen while the RAM, the timers, the
serial port and the interrupt system continue to function.
In the power down mode the RAM is saved and all other
functions are inoperative.
The 80C32 is identical to the 80C52 except that it has no
on-chip ROM. TEMIC’s 80C52/80C32 are
manufactured using SCMOS process which allows them
to run from 0 up to 44 MHz with VCC = 5 V.
TEMIC’s 80C52 and 80C32 are also available at
16 MHz with 2.7 V < VCC < 5.5 V.
D 80C32-40: 0 to 40 MHz(1)
D 80C32-42: 0 to 42 MHz(1)
D 80C32-44: 0 to 44 MHz(1)
Notes:
1. 0 to 70_C temperature range.
2. For other speed and temperature range availability, please
contact your sales office.
2. Features
D Power control modes
D 256 bytes of RAM
D 8 Kbytes of ROM (80C52)
D 32 programmable I/O lines
D Three 16 bit timer/counters
D 64 K program memory space
D 64 K data memory space
D Fully static design
D 0.8µ CMOS process
D Boolean processor
D 6 interrupt sources
D Programmable serial port
D Temperature range: commercial, industrial, automotive,
military
3. Optional
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D Secret ROM: Encryption
D Secret TAG: Identification number
Rev. I September 18, 1998
1

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P-80C32 pdf, ピン配列
www.DataSheet4U.com
80C32/80C52
DIL
P1.5
P1.6
P1.7
RST
RxD/P3.0
NC
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 35
12
80C32/80C52
34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
P0.4/A4
P0.5/A5
P0.6/A6
P0.7/A7
EA
NC
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
LCC
P1.5
P1.6
P1.7
RST
RxD/P3.0
NC
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
80C32/80C52
P0.4/A4
P0.5/A5
P0.6/A6
P0.7/A7
EA
NC
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
QFP
Diagrams are for reference only. Package sizes are not to scale.
www.DataSheet4U.com
Figure 2. Pin Configuration
Rev. I September 18, 1998
3


3Pages


P-80C32 電子部品, 半導体
www.DataSheet4U.com
80C32/80C52
6. Idle And Power Down Operation
Figure 3. shows the internal Idle and Power Down clock configuration. As illustrated, Power Down operation stops
the oscillator. Idle mode operation allows the interrupt, serial port, and timer blocks to continue to function, while the
clock to the CPU is gated off.
These special modes are activated by software via the Special Function Register, PCON. Its hardware address is 87H.
PCON is not bit addressable.
Figure 3. Idle and Power Down Hardware
PCON: Power Control Register
(MSB)
76
SMOD
5
(LSB)
43210
– GF1 GF0 PD IDL
Symbol Position
Name and Function
SMOD
PCON.7
Double Baud rate bit
When set to a 1, the baud rate is doubled when the serial port is being used in either modes 1, 2 or 3.
Reserved
– PCON.6
The value read from this bit is indeterminate. Do not set this bit.
Reserved
– PCON.5
The value read from this bit is indeterminate. Do not set this bit.
Reserved
– PCON.4
The value read from this bit is indeterminate. Do not set this bit.
GF1 PCON.3 General–purpose flag bit
GF0 PCON.2 General–purpose flag bit
PD(1)
PCON.1
Power Down bit. Setting this bit activates power down operation
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Power–Down mode.
If IDL and PD are both set, PD takes precedence.
Idle mode bit
IDL(1)
PCON.0
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Idle mode.
www.DataSheet4U.comIf IDL and PD are both set, PD takes precedence.
1. If 1’s are written to PD and IDL at the same time. PD takes, precedence. The reset value of PCON is (000X0000).
6 Rev. I September 18, 1998

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
P-80C31

P80C31

NXP Semiconductors
NXP Semiconductors
P-80C32

P80C32

ETC
ETC
P-80C32

(P-80C32 / P-80C52) CMOS 8-Bit Microcontroller

Temic
Temic


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