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MC74AC256 の電気的特性と機能

MC74AC256のメーカーはMotorola Semiconductorsです、この部品の機能は「DUAL 4-BIT ADDRESSABLE LATCH」です。


製品の詳細 ( Datasheet PDF )

部品番号 MC74AC256
部品説明 DUAL 4-BIT ADDRESSABLE LATCH
メーカ Motorola Semiconductors
ロゴ Motorola Semiconductors ロゴ 




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MC74AC256 Datasheet, MC74AC256 PDF,ピン配置, 機能
( DataSheet : www.DataSheet4U.com )
MC74AC256
MC74ACT256
Dual 4ĆBit Addressable Latch
The MC74AC256/74ACT256 dual addressable latch has four distinct modes
of operation which are selectable by controlling the Clear and Enable inputs
(see Function Table). In the addressable latch mode, data at the Data (D) inputs
is written into the addressed latches. The addressed latches will follow the Data
input with all unaddressed latches remaining in their previous states.
In the memory mode, all latches remain in their previous states and are
unaffected by the Data or Address inputs. To eliminate the possibility of entering
erroneous data in the latches, the enable should be held HIGH (inactive) while
the address lines are changing. In the dual 1-of-4 decoding or demultiplexing
mode (MR = E = LOW), addressed outputs will follow the level of the D inputs
with all other outputs LOW. In the clear mode, all outputs are LOW and unaffected
by the Address and Data inputs.
Combines Dual Demultiplexer and 8-Bit Latch
Serial-to-Parallel Capability
Output from Each Storage Bit Available
Random (Addressable) Data Entry
Easily Expandable
Common Clear Input
Useful as Dual 1-of-4 Active HIGH Decoder
VCC MR E Db Q3b Q2b Q1b Q0b
16 15 14 13 12 11 10 9
DUAL 4-BIT
ADDRESSABLE
LATCH
N SUFFIX
CASE 648-08
PLASTIC
D SUFFIX
CASE 751B-05
PLASTIC
12345678
A0 A1 Da Q0a Q1a Q2a Q3a GND
LOGIC SYMBOL
Da Db
A0
E
A1 MR
Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b
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FACT DATA
5-1
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1 Page





MC74AC256 pdf, ピン配列
MC74AC256 MC74ACT256
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min Typ
VCC
Supply Voltage
AC
ACT
2.0 5.0
4.5 5.0
Vin, Vout
tr, tf
DC Input Voltage, Output Voltage (Ref. to GND)
Input Rise and Fall Time (Note 1)
AC Devices except Schmitt Inputs
Input Rise and Fall Time (Note 2)
tr, tf ACT Devices except Schmitt Inputs
TJ Junction Temperature (PDIP)
TA Operating Ambient Temperature Range
IOH Output Current — High
IOL Output Current — Low
VCC @ 3.0 V
VCC @ 4.5 V
VCC @ 5.5 V
VCC @ 4.5 V
VCC @ 5.5 V
0
–40
150
40
25
10
8.0
25
1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
DC CHARACTERISTICS
74AC
74AC
Symbol
Parameter
VCC
(V)
TA = +25°C
TA =
–40°C to +85°C
Unit
Typ Guaranteed Limits
VIH Minimum High Level
Input Voltage
3.0 1.5 2.1
4.5 2.25 3.15
5.5 2.75 3.85
2.1
3.15
3.85
V
VIL
VOH
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
3.0 1.5 0.9
4.5 2.25 1.35
5.5 2.75 1.65
3.0 2.99 2.9
4.5 4.49 4.4
5.5 5.49 5.4
0.9
1.35
1.65
2.9
4.4
5.4
V
V
VOL
Maximum Low Level
Output Voltage
3.0 2.56
4.5 3.86
5.5 4.86
3.0 0.002 0.1
4.5 0.001 0.1
5.5 0.001 0.1
2.46
3.76
4.76
0.1
0.1
0.1
V
V
IIN Maximum Input
Leakage Current
3.0 0.36 0.44
4.5 0.36 0.44
5.5 0.36 0.44
5.5 ±0.1 ±1.0
IOLD
IOHD
ICC
†Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
5.5 75
5.5 –75
5.5 8.0 80
* All outputs loaded; thresholds on input associated with output under test.
† Maximum test duration 2.0 ms, one output loaded at a time.
Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
V
µA
mA
mA
µA
Max
6.0
5.5
VCC
Unit
V
V
ns/V
ns/V
140 °C
85 °C
–24 mA
24 mA
Conditions
VOUT = 0.1 V
or VCC – 0.1 V
VOUT = 0.1 V
or VCC – 0.1 V
IOUT = –50 µA
*VIN = VIL or VIH
–12 mA
IOH –24 mA
–24 mA
IOUT = 50 µA
*VIN = VIL or VIH
12 mA
IOL 24 mA
24 mA
VI = VCC, GND
VOLD = 1.65 V Max
VOHD = 3.85 V Min
VIN = VCC or GND
FACT DATA
5-3


3Pages


MC74AC256 電子部品, 半導体
MC74AC256 MC74ACT256
AC CHARACTERISTICS (For Figures and Waveforms — See Section 3)
74ACT
Symbol
Parameter
VCC*
(V)
TA = +25°C
CL = 50 pF
tPLH
tPHL
Propagation Delay
Dn to Qn
Propagation Delay
Dn to Qn
tPLH
Propagation Delay
E to Qn
tPHL
tPLH
Propagation Delay
E to Qn
Propagation Delay
Address to Qn
tPHL
Propagation Delay
Address to Qn
tPHL
Propagation Delay
MR to Q
* Voltage Range 5.0 V is 5.0 V ±0.5 V.
Min Typ Max
5.0 2.0 6.5 11.5
5.0 2.0 7.0 11.0
5.0 2.0 8.0 12.0
5.0 2.0 6.5 10.5
5.0 2.0 10.5 14.5
5.0 2.0 9.0 12.5
5.0 2.0 7.0 10.5
74ACT
TA = –40°C
to +85°C
CL = 50 pF
Min Max
1.5 13.0
1.5 12.5
1.5 14.0
1.5 12.5
1.5 17.0
1.5 14.5
1.5 11.5
Unit
ns
ns
ns
ns
ns
ns
ns
Fig.
No.
3-5
3-5
3-6
3-6
3-6
3-6
3-7
AC OPERATING REQUIREMENTS
Symbol
Parameter
ts
Setup Time, HIGH or LOW
Dn to E
th
Hold Time, HIGH or LOW
Dn to E
ts
Setup Time
Address to E
th
Hold Time
Address to E
* Voltage Range 5.0 V is 5.0 V ±0.5 V.
74ACT
74ACT
VCC*
(V)
TA = +25°C
CL = 50 pF
TA = –40°C
to +85°C
CL = 50 pF
Unit
Fig.
No.
Typ Guaranteed Minimum
5.0 3.5 4.5 ns 3-9
5.0 2.5 2.5 ns 3-9
5.0 5.5 6.5 ns 3-6
5.0 2.5 2.5 ns 3-6
CAPACITANCE
Symbol
Parameter
CIN
CPD
Input Capacitance
Power Dissipation Capacitance
Value
Typ
4.5
30.0
Unit
pF
pF
Test Conditions
VCC = 5.0 V
VCC = 5.0 V
FACT DATA
5-6

6 Page



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共有リンク

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