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STP10NA40FIのメーカーはST Microelectronicsです、この部品の機能は「N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR」です。 |
部品番号 | STP10NA40FI |
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部品説明 | N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR | ||
メーカ | ST Microelectronics | ||
ロゴ | |||
このページの下部にプレビューとSTP10NA40FIダウンロード(pdfファイル)リンクがあります。 Total 10 pages
( DataSheet : www.DataSheet4U.com )
STP10NA40
STP10NA40FI
N - CHANNEL ENHANCEMENT MODE
FAST POWER MOS TRANSISTOR
TYPE
STP10NA40
STP10NA40FI
VDSS
400 V
400 V
RDS(on)
< 0.55 Ω
< 0.55 Ω
ID
10 A
6A
s TYPICAL RDS(on) = 0.46 Ω
s ± 30V GATE TO SOURCE VOLTAGE RATING
s 100% AVALANCHE TESTED
s REPETITIVE AVALANCHE DATA AT 100oC
s LOW INTRINSIC CAPACITANCES
s GATE GHARGE MINIMIZED
s REDUCED THRESHOLD VOLTAGE SPREAD
DESCRIPTION
This series of POWER MOSFETS represents the
most advanced high voltage technology. The
optimized cell layout coupled with a new
proprietary edge termination concur to give the
device low RDS(on) and gate charge, unequalled
ruggedness and superior switching performance.
APPLICATIONS
s HIGH CURRENT, HIGH SPEED SWITCHING
s SWITCH MODE POWER SUPPLIES (SMPS)
s DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDS Drain-source Voltage (VGS = 0)
VDGR Drain-gate Voltage (RGS = 20 kΩ)
VGS Gate-source Voltage
ID Drain Current (continuous) at Tc = 25 oC
ID Drain Current (continuous) at Tc = 100 oC
IDM(•) Drain Current (pulsed)
Ptot Total Dissipation at Tc = 25 oC
Derating Factor
VISO Insulation Withstand Voltage (DC)
Tstg Storage Temperature
Tj Max. Operating Junction Temperature
(•) Pulse width limited by safe operating area
November 1996
3
2
1
TO-220
3
2
1
ISOWATT220
INTERNAL SCHEMATIC DIAGRAM
Value
STP10NA40
STP10NA40FI
400
400
± 30
10 6
6.3 3.8
40 40
125 45
1 0.36
2000
-65 to 150
150
Unit
V
V
V
A
A
A
W
W/oC
V
oC
oC
1/10
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1 Page STP10NA40/FI
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbol
td(on)
tr
Parameter
Turn-on Time
Rise Time
(di/dt)on Turn-on Current Slope
Qg Total Gate Charge
Qgs Gate-Source Charge
Qgd Gate-Drain Charge
Test Conditions
VDD = 200 V ID = 5 A
RG = 47 Ω
VGS = 10 V
(see test circuit, figure 3)
VDD = 320 V ID = 10 A
RG = 47 Ω
VGS = 10 V
(see test circuit, figure 5)
VDD = 320 V ID = 10 A VGS = 10 V
Min.
Typ.
35
115
250
54
8
27
Max.
50
155
75
Unit
ns
ns
A/µs
nC
nC
nC
SWITCHING OFF
Symbol
tr(Voff)
tf
tc
Parameter
Off-voltage Rise Time
Fall Time
Cross-over Time
Test Conditions
VDD = 320 V ID = 10 A
RG = 47 Ω VGS = 10 V
(see test circuit, figure 5)
Min.
Typ.
75
30
120
Max.
105
45
160
Unit
ns
ns
ns
SOURCE DRAIN DIODE
Symbol
Parameter
Test Conditions
ISD
ISDM(•)
Source-drain Current
Source-drain Current
(pulsed)
VSD (∗) Forward On Voltage
ISD = 10 A VGS = 0
trr Reverse Recovery
Time
Qrr Reverse Recovery
Charge
ISD = 10 A di/dt = 100 A/µs
VDD = 100 V Tj = 150 oC
(see test circuit, figure 5)
IRRM
Reverse Recovery
Current
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
Min.
Typ.
Max.
10
40
Unit
A
A
470
6.5
27.5
1.6
V
ns
µC
A
Safe Operating Areas for TO-220
Safe Operating Areas for ISOWATT220
3/10
3Pages STP10NA40/FI
Turn-on Current Slope
Turn-off Drain-source Voltage Slope
Cross-over Time
Switching Safe Operating Area
Accidental Overload Area
Source-drain Diode Forward Characteristics
6/10
6 Page | |||
ページ | 合計 : 10 ページ | ||
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部品番号 | 部品説明 | メーカ |
STP10NA40FI | N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR | ST Microelectronics |