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ST90135 の電気的特性と機能

ST90135のメーカーはST Microelectronicsです、この部品の機能は「(ST90135 / ST90158) Microcontroller」です。


製品の詳細 ( Datasheet PDF )

部品番号 ST90135
部品説明 (ST90135 / ST90158) Microcontroller
メーカ ST Microelectronics
ロゴ ST Microelectronics ロゴ 




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ST90135 Datasheet, ST90135 PDF,ピン配置, 機能
ST90158 - ST90135
8/16-BIT MCU FAMILY WITH
UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM
s Register File based 8/16 bit Core Architecture
with RUN, WFI, SLOW and HALT modes
s Internal Memory:
– EPROM/OTP/ROM 24/32/48/64K bytes
– ROMless version available
– RAM 768/1K/1.5K/2K bytes
s Maximum External Memory: 64K bytes
s 224 general purpose registers available as
RAM, accumulators or index pointers (register
file)
s 67 fully programmable I/O bits
s Fully Programmable PLL Clock Generator, with
Frequency Multiplication and low frequency,
low cost external crystal
s Minimum 8-bit Instruction Cycle time: 83ns - (@
24 MHz internal clock frequency)
s Minimum 16-bit Instruction Cycle time: 250ns -
(@ 24 MHz internal clock frequency)
s 8 external and 1 Non-Maskable Interrupts
s DMA Controller and Programmable Interrupt
Handler
s Single Master Serial Peripheral Interface with
I2C capability
s Two 16-bit Timers with 8-bit Prescaler, one
usable as a Watchdog Timer (software and
hardware)
s Three (ST90158) or two (ST90135) 16-bit
Multifunction Timers, each with an 8 bit
prescaler, 12 operating modes and DMA
capabilities
s 8 channel 8-bit Analog to Digital Converter, with
Automatic voltage monitoring capabilities and
external reference inputs
DEVICE SUMMARY
TQFP80
PQFP80
s Two (ST90158) or one (ST90135) Serial
Communication Interfaces with asynchronous,
synchronous and DMA capabilities
s Rich Instruction Set with 14 Addressing modes
s Division-by-Zero trap generation
s Versatile IDE (Integrated development
Environment) including Assembler, Linker, C-
compiler, Archiver, Source Level Debugger
s Hardware tools; Real Time Emulator, EPROM
Programming Board
s Gang Programmer and Real Time Operating
System available from Third parties
Features
ST90135M5 ST90135M6 ST90158M7 ST90158M9 ST90R158 ST90T158 ST90T158LV
Program Memory 24K ROM
32K ROM 48K ROM 64K ROM ROMless 64K OTP 64K OTP
RAM
768 1K 1.5K 2K 2K 2K 2K
Operating Supply
2.7V to 5.5V
3.3V to 5.5V 2.7V to 3.3V
CPU Frequency
Peripherals
Operating
Temperature
Up to 24MHz (for 4.5V<VDD<5.5V); Up to 16MHz (for 2.7V<VDD<4.5V)
Watchdog Timer, Two Multi-
function Timers, One SCI, One
SPI, ADC, 16-bit Timer
Watchdog Timer, Three Multifunction Timers, Two SCI, One SPI,
ADC, 16-bit timer
-45°C to 85°C
Packages
PQ FP8 0/TQF P80
Rev. 3.1
June 2000
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ST90135 pdf, ピン配列
Table of Contents
4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.2 INTERRUPT VECTORING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.2.1 Divide by Zero trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.2.2 Segment Paging During Interrupt Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.3 INTERRUPT PRIORITY LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.4 PRIORITY LEVEL ARBITRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.4.1 Priority level 7 (Lowest) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.4.2 Maximum depth of nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.4.3 Simultaneous Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.4.4 Dynamic Priority Level Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.5 ARBITRATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.5.1 Concurrent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.5.2 Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.7 TOP LEVEL INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.8 ON-CHIP PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.9 INTERRUPT RESPONSE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.10 INTERRUPT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5 ON-CHIP DIRECT MEMORY ACCESS (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.2 DMA PRIORITY LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3 DMA TRANSACTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.4 DMA CYCLE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.5 SWAP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.6 DMA REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6 RESET AND CLOCK CONTROL UNIT (RCCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.2 CLOCK CONTROL UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.2.1 Clock Control Unit Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3 CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.1 PLL Clock Multiplier Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3.2 CPU Clock Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3.3 Peripheral Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.3.5 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.4 CLOCK CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.5 OSCILLATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.6 RESET/STOP MANAGER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.6.1 RESET Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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3Pages


ST90135 電子部品, 半導体
ST90158 - GENERAL DESCRIPTION
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST90158 and ST90135 microcontrollers are
developed and manufactured by STMicroelectron-
ics using a proprietary n-well CMOS process.
Their performance derives from the use of a flexi-
ble 256-register programming model for ultra-fast
context switching and real-time event response.
The intelligent on-chip peripherals offload the ST9
core from I/O and data management processing
tasks allowing critical application tasks to get the
maximum use of core resources. The new-gener-
ation ST9 MCU devices now also support low
power consumption and low voltage operation for
power-efficient and low-cost embedded systems.
1.1.1 ST9 Core
The advanced Core consists of the Central
Processing Unit (CPU), the Register File, the Inter-
rupt and DMA controller, and the Memory Man-
agement Unit (MMU). The MMU allows address-
ing of up to 4 Megabytes of program and data
mapped into a single linear space.
Four independent buses are controlled by the
Core: a 16-bit memory bus, an 8-bit register data
bus, an 8-bit register address bus and a 6-bit inter-
rupt/DMA bus which connects the interrupt and
DMA controllers in the on-chip peripherals with the
core.
This multiple bus architecture makes the ST9 fam-
ily devices highly efficient for accessing on and off-
chip memory and fast exchange of data with the
on-chip peripherals.
The general-purpose registers can be used as ac-
cumulators, index registers, or address pointers.
Adjacent register pairs make up 16-bit registers for
addressing or 16-bit processing. Although the ST9
has an 8-bit ALU, the chip handles 16-bit opera-
tions, including arithmetic, loads/stores, and mem-
ory/register and memory/memory exchanges.
1.1.2 Power Saving Modes
To optimize performance versus power consump-
tion, a range of operating modes can be dynami-
cally selected.
Run Mode. This is the full speed execution mode
with CPU and peripherals running at the maximum
clock speed delivered by the Phase Locked Loop
(PLL) of the Clock Control Unit (CCU).
Slow Mode. Power consumption can be signifi-
cantly reduced by running the CPU and the periph-
erals at reduced clock speed using the CPU Pres-
caler and CCU Clock Divider (PLL not used) or by
using the CK_AF external clock.
Wait For Interrupt Mode. The Wait For Interrupt
(WFI) instruction suspends program execution un-
til an interrupt request is acknowledged. During
WFI, the CPU clock is halted while the peripheral
and interrupt controller keep running at a frequen-
cy programmable via the CCU.
Halt Mode. When executing the HALT instruction,
and if the Watchdog is not enabled, the CPU and
its peripherals stop operating and the status of the
machine remains frozen (the clock is also
stopped). A reset is necessary to exit from Halt
mode.
1.1.3 System Clock
A programmable PLL Clock Generator allows
standard 3 to 5 MHz crystals to be used to obtain a
large range of internal frequencies up to 16 MHz or
24 MHz, depending on device.
1.1.4 I/O Ports
The I/O lines are grouped into up to nine 8-bit I/O
Ports and can be configured on a bit basis to pro-
vide timing, status signals, an address/data bus for
interfacing to external memory, timer inputs and
outputs, analog inputs, external interrupts and se-
rial or parallel I/O.
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共有リンク

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部品番号部品説明メーカ
ST9013

NPN Silicon Epitaxial Planar Transistor

SEMTECH
SEMTECH
ST90135

(ST90135 / ST90158) Microcontroller

ST Microelectronics
ST Microelectronics


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