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PDF MT55L256V36F Data sheet ( Hoja de datos )
| Número de pieza | MT55L256V36F | |
| Descripción | (MT55LxxxLxxF) 8Mb SRAM | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
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8Mb
ZBT® SRAM
8Mb: 512K x 18, 256K x 32/36
FLOW-THROUGH ZBT SRAM
MT55L512L18F, MT55L512V18F,
MT55L256L32F, MT55L256V32F,
MT55L256L36F, MT55L256V36F
3.3V VDD, 3.3V or 2.5V I/O
FEATURES
• High frequency and 100 percent bus utilization
• Fast cycle times: 10ns, 11ns and 12ns
• Single +3.3V ±5% power supply (VDD)
• Separate +3.3V or +2.5V isolated output buffer
supply (VDDQ)
• Advanced control logic for minimum control
signal interface
• Individual BYTE WRITE controls may be tied LOW
• Single R/W# (read/write) control pin
• CKE# pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• Clock-controlled and registered addresses, data
I/Os and control signals
• Internally self-timed, fully coherent WRITE
• Internally self-timed, registered outputs to
eliminate the need to control OE#
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Linear or Interleaved Burst Modes
• Burst feature (optional)
• Pin/function compatibility with 2Mb, 4Mb, and
18Mb ZBT SRAM
• 100-pin TQFP
• 165-pin FBGA
• Automatic power-down
OPTIONS
• Timing (Access/Cycle/MHz)
7.5ns/10ns/100 MHz
8.5ns/11ns/90 MHz
9ns/12ns/83 MHz
MARKING
-10
-11
-12
• Configurations
3.3V I/O
512K x 18
256K x 32
256K x 36
2.5V I/O
512K x 18
256K x 32
256K x 36
• Package
100-pin TQFP
165-pin FBGA
MT55L512L18F
MT55L256L32F
MT55L256L36F
MT55L512V18F
MT55L256V32F
MT55L256V36F
T
F*
• Operating Temperature Range
Commercial (0ºC to +70ºC)
Industrial (-40°C to +85°C)**
None
IT
Part Number Example:
MT55L256L32FT-11
100-Pin TQFP1
165-Pin FBGA
NOTE: 1. JEDEC-standard MS-026 BHA (LQFP).
* A Part Marking Guide for the FBGA devices can be found on Micron’s
Web site—http://www.micron.com/support/index.html.
** Industrial temperature range offered in specific speed grades and
configurations. Contact factory for more information.
GENERAL DESCRIPTION
The Micron® Zero Bus Turnaround™ (ZBT®) SRAM
family employs high-speed, low-power CMOS designs
using an advanced CMOS process.
Micron’s 8Mb ZBT SRAMs integrate a 512K x 18,
256K x 32, or 256K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. These SRAMs are optimized for 100 percent
bus utilization, eliminating any turnaround cycles for
READ to WRITE, or WRITE to READ, transitions. All
synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input (CLK).
The synchronous inputs include all addresses, all data
inputs, chip enable (CE#), two additional chip enables
for easy depth expansion (CE2, CE2#), cycle start input
8Mb: 512K x 18, 256K x 32/36 Flow-Through ZBT SRAM
MT55L512L18F_C.p65 – Rev. 2/02
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
www.DataSheet4U.com
1 page  
8Mb: 512K x 18, 256K x 32/36
FLOW-THROUGH ZBT SRAM
PIN ASSIGNMENT (TOP VIEW)
100-PIN TQFP
SA
SA
SA
NF3
ADV/LD#
OE# (G#)
CKE#
R/W#
CLK
VSS
VDD
CE2#
BWa#
BWb#
NC
NC
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81 50
82 49
83 48
84 47
85 46
86 45
87 44
88 43
89 42
x1890 41
91 40
92 39
93 38
94 37
95 36
96 35
97 34
98 33
99 32
100 31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SA
SA
SA
SA
SA
SA
SA
DNU
DNU
VDD
VSS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
SA
SA
SA
NF3
ADV/LD#
OE# (G#)
CKE#
R/W#
CLK
VSS
VDD
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81 50
82 49
83 48
84 47
85 46
86 45
87 44
88 43
89 42
x32/x3690 41
91 40
92 39
93 38
94 37
95 36
96 35
97 34
98 33
99 32
100 31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SA
SA
SA
SA
SA
SA
SA
DNU
DNU
VDD
VSS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
NOTE:
1. Pins 14 and 66 do not have to be connected directly to VSS if the input voltage is ≤ VIL.
2. Pins 16 does not have to be connected directly to VDD if the input voltage is ≥ VIH.
3. Pin 84 is reserved for address expansion to 18Mb device.
4. NF for x32 version, DQPx for x36 version.
8Mb: 512K x 18, 256K x 32/36 Flow-Through ZBT SRAM
MT55L512L18F_C.p65 – Rev. 2/02
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
5 Page 
8Mb: 512K x 18, 256K x 32/36
FLOW-THROUGH ZBT SRAM
FBGA PIN DESCRIPTIONS (continued)
x18 x32/x36 SYMBOL TYPE
DESCRIPTION
1H, 4C, 4N, 1H, 4C, 4N,
VSS Supply Ground: GND.
5C, 5D, 5E, 5F, 5C, 5D, 5E, 5F,
5G, 5H, 5J, 5G, 5H, 5J,
5K, 5L, 5M, 5K, 5L, 5M,
6C, 6D, 6E, 6F, 6C, 6D, 6E, 6F,
6G, 6H, 6J, 6G, 6H, 6J,
6K, 6L, 6M, 6K, 6L, 6M,
7C, 7D, 7E, 7C, 7D, 7E,
7F, 7G, 7H, 7F, 7G, 7H,
7J, 7K, 7L, 7J, 7K, 7L,
7M, 7N, 8C, 8N 7M, 7N, 8C, 8N
5P, 5R, 7P, 7R 5P, 5R, 7P, 7R DNU
– Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
1A, 1B, 1C,
1D, 1E, 1F,
1G, 1P, 2C,
2J, 2K, 2L,
2M, 2N, 2P,
2R, 3H, 4B,
9B, 5A, 5N,
6N, 9H, 10C,
10D, 10E,
10F, 10G,
10H, 10N,
11B, 11J,
11K, 11L,
11M, 11N,
11P
1A, 1B, 1P,
2C, 2N, 2P,
2R, 3H, 5N,
6N, 9B, 9H,
10C, 10H,
10N, 11A,
11B, 11P
NC
– No Connect: These signals are not internally connected and may
be connected to ground to improve package heat dissipation.
Pin 9B is reserved for 16MB address expansion.
NF — No Function: These pins are internally connected to the die and
have the capacitance of an input pin. It is allowable to leave
these pins unconnected or driven by signals.
8Mb: 512K x 18, 256K x 32/36 Flow-Through ZBT SRAM
MT55L512L18F_C.p65 – Rev. 2/02
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet MT55L256V36F.PDF ] | |
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