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PDF MT58L64V32P Data sheet ( Hoja de datos )
| Número de pieza | MT58L64V32P | |
| Descripción | (MT58LxxxxP) 2Mb SRAM | |
| Fabricantes | Micron Semiconductor | |
| Logotipo |  |
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NOT RECOMENDED FOR NEW DESIGNS
2SMRAbMtSaSYhNeeCt4BUU.coRmST™
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
MT58L128L18P, MT58L64L32P, MT58L64L36P;
MT58L128V18P, MT58L64V32P, MT58L64V36P
3.3V VDD, 3.3V or 2.5V I/O, Pipelined, Single-
Cycle Deselect
.DaFEATURES
w• Fast clock and OE# access times
• Single +3.3V +0.3V/-0.165V power supply (VDD)
w• Separate +3.3V or +2.5V isolated output buffer
w supply (VDDQ)
m• SNOOZE MODE for reduced-power standby
• Single-cycle deselect (Pentium® BSRAM-compatible)
o• Common data inputs and data outputs
.c• Individual BYTE WRITE control and GLOBAL
WRITE
• Three chip enables for simple depth expansion
Uand address pipelining
• Clock-controlled and registered addresses, data
t4I/Os and control signals
• Internally self-timed WRITE cycle
• Burst control pin (interleaved or linear burst)
e• Automatic power-down for portable applications
e• 100-pin TQFP package
• Low capacitive bus loading
h• x18, x32, and x36 options available
SOPTIONS
ta• Timing (Access/Cycle/MHz)
3.5ns/5ns/200 MHz
3.5ns/6ns/166 MHz
a4.0ns/7.5ns/133 MHz
5ns/10ns/100 MHz
.D• Configurations
3.3V I/O
w128K x 18
64K x 32
64K x 36
w2.5V I/O
m128K x 18
w o64K x 32
.c64K x 36
t4U• Package
100-pin TQFP
hee• Operating Temperature Range
SCommercial (0°C to +70°C)
MARKING
-5
-6
-7.5
-10
MT58L128L18P
MT58L64L32P
MT58L64L36P
MT58L128V18P
MT58L64V32P
MT58L64V36P
T
None
ataPart Number Example:
.DMT58L128L18PT-10
100-Pin TQFP*
*JEDEC-standard MS-026 BHA (LQFP).
GENERAL DESCRIPTION
The Micron® SyncBurst™ SRAM family employs
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
Micron’s 2Mb SyncBurst SRAMs integrate a 128K x
18, 64K x 32, or 64K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single clock
input (CLK). The synchronous inputs include all
addresses, all data inputs, active LOW chip enable (CE#),
two additional chip enables for easy depth expansion
(CE2, CE2#), burst control inputs (ADSC#, ADSP#,
ADV#), byte write enables (BWx#), and global write
(GW#).
Asynchronous inputs include the output enable
(OE#), clock (CLK), and snooze enable (ZZ). There is
also a burst mode pin (MODE) that selects between
interleaved and linear burst modes. The data-out (Q),
enabled by OE#, is also asynchronous. WRITE cycles
can be from one to two bytes wide (x18) or from one
to four bytes wide (x32/x36), as controlled by the write
control inputs.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) input pins. Subsequent burst addresses can be
internally generated as controlled by the burst advance
pin (ADV#).
ww2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
wMT58L128L18P_C.p65 – Rev. C, Pub. 11/02
1
©2002, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
1 page  
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
TQFP PIN DESCRIPTIONS
x18 x32/x36 SYMBOL
37 37
36 36
32-35, 44-49, 32-35, 44-49,
80-82, 99, 81, 82, 99,
100 100
SA0
SA1
SA
93 93 BWa#
94 94 BWb#
– 95 BWc#
– 96 BWd#
87 87 BWE#
88 88 GW#
89 89 CLK
98 98 CE#
92 92 CE2#
97 97 CE2
86 86 OE#
83 83 ADV#
84 84 ADSP#
TYPE
DESCRIPTION
Input Synchronous Address Inputs: These inputs are registered and must
meet the setup and hold times around the rising edge of CLK.
Input
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa pins and DQPa; BWb# controls DQb pins and
DQPb. For the x32 and x36 versions, BWa# controls DQa pins and
DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. Parity is only
available on the x18 and x36 versions.
Input Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the
rising edge of CLK.
Input Global Write: This active LOW input allows a full 18-, 32-, or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
Input
Clock: This signal registers the address, data, chip enable, byte write
enables, and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
Input Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
Input Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
Input Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
Input Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
Input
Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after the
external address is loaded. A HIGH on this pin effectively causes wait
states to be generated (no address advance). To ensure use of
correct address during a WRITE cycle, ADV# must be HIGH at the
rising edge of the first clock after an ADSP# cycle is initiated.
Input
Synchronous Address Status Processor: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent
upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is HIGH. Power-
down state is entered if CE2 is LOW or CE2# is HIGH.
(continued)
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L128L18P_C.p65 – Rev. C, Pub. 11/02
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
5 Page 
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
IDD OPERATING CONDITIONS AND MAXIMUM LIMITS
(Note 1) (0°C ≤ TA ≤ +70°C; VDD = +3.3V +0.3V/-0.165V unless otherwise noted)
MAX
DESCRIPTION
CONDITIONS
SYM TYP -5 -6 -7.5
Power Supply
Current:
Operating
Device selected; All inputs ≤ VIL
or ≥ VIH; Cycle time ≥ tKC (MIN);
VDD = MAX; Outputs open
IDD 100 400 340 280
Power Supply
Current: Idle
Device selected; VDD = MAX;
ADSC#, ADSP#, GW#, BWx#, ADV# ≥
VIH; All inputs ≤ VSS + 0.2 or ≥ VDD - 0.2;
Cycle time ≥ tKC (MIN)
IDD1
30 100 85
70
CMOS Standby
Device deselected; VDD = MAX;
All inputs ≤ VSS + 0.2 or ≥ VDD - 0.2;
All inputs static; CLK frequency = 0
ISB2 0.5 10 10 10
TTL Standby
Device deselected; VDD = MAX;
All inputs ≤ VIL or ≥ VIH;
ISB3 6 25 25 25
All inputs static; CLK frequency = 0
Clock Running
Device deselected; VDD = MAX;
ADSC#, ADSP#, GW#, BWx#, ADV# ≥
VIH; All inputs ≤ VSS + 0.2 or ≥ VDD - 0.2;
Cycle time ≥ tKC (MIN)
ISB4
30 100 85 70
-10 UNITS NOTES
225 mA 2, 3, 4
65 mA 2, 3, 4
10 mA 3, 4
25 mA 3, 4
65 mA 3, 4
TQFP CAPACITANCE
DESCRIPTION
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
Clock Capacitance
CONDITIONS
TA = 25°C; f = 1 MHz;
VDD = 3.3V
SYMBOL
CI
CO
CA
CCK
TYP
2.7
4
2.5
2.5
MAX
3.5
5
3.5
3.5
UNITS
pF
pF
pF
pF
NOTES
5
5
5
5
NOTE:
1. VDDQ = +3.3V +0.3V/-0.165V for 3.3V I/O configuration; VDDQ = +2.5V +0.4V/-0.125V for 2.5V I/O configuration.
2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times
and greater output loading.
3. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means device
is active (not in power-down mode).
4. Typical values are measured at 3.3V, 25°C and 10ns cycle time.
5. This parameter is sampled.
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L128L18P_C.p65 – Rev. C, Pub. 11/02
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MT58L64V32P.PDF ] | |
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