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PDF MT58L64L36D Data sheet ( Hoja de datos )
| Número de pieza | MT58L64L36D | |
| Descripción | (MT58LxxxLxxD) 2Mb SRAM | |
| Fabricantes | Micron Semiconductor | |
| Logotipo |  |
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.comNOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36
PIPELINED, DCD SYNCBURST SRAM
et4U ™ MT58L128L18D, MT58L64L32D,
2Mb SYNe CBURST MT58L64L36D
SRAM Sh 3.3V VDD, 3.3V I/O, Pipelined, Double-Cycle
ta Deselect
.DaFEATURES
w• Fast clock and OE# access times
w• Single +3.3V +0.3V/-0.165V power supply (VDD)
w• Separate +3.3V isolated output buffer supply
m(VDDQ)
• SNOOZE MODE for reduced-power standby
o• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL
.cWRITE
• Three chip enables for simple depth expansion and
address pipelining
U• Clock-controlled and registered addresses, data
t4I/Os and control signals
• Internally self-timed WRITE cycle
• Burst control pin (interleaved or linear burst)
e• Automatic power-down
• 100-pin TQFP package
e• Low capacitive bus loading
h• x18, x32, and x36 options available
OPTIONS
S• Timing (Access/Cycle/MHz)
ta3.5ns/6ns/166 MHz
4.0ns/7.5ns/133 MHz
5ns/10ns/100 MHz
a• Configurations
128K x 18
.D64K x 32
64K x 36
• Packages
w100-pin TQFP
• Operating Temperature Range
wCommercial (0°C to +70°C)
MARKING
-6
-7.5
-10
MT58L128L18D
MT58L64L32D
MT58L64L36D
T
None
w omPart Number Example:
.cMT58L128L18DT-10
t4UGENERAL DESCRIPTION
eThe Micron® SyncBurst™ SRAM family employs
hehigh- speed, low-power CMOS designs that are fabri-
Scated using an advanced CMOS process.
taMicron’s 2Mb SyncBurst SRAMs integrate a 128K x
18, 64K x 32, or 64K x 36 SRAM core with advanced
asynchronous peripheral circuitry and a 2-bit burst
.Dcounter. All synchronous inputs pass through registers
100-Pin TQFP*
*JEDEC-standard MS-026 BHA (LQFP).
controlled by a positive-edge-triggered single clock
input (CLK). The synchronous inputs include all ad-
dresses, all data inputs, active LOW chip enable (CE#),
two additional chip enables for easy depth expansion
(CE2, CE2#), burst control inputs (ADSC#, ADSP#,
ADV#), byte write enables (BWx#) and global write
(GW#).
Asynchronous inputs include the output enable
(OE#), clock (CLK) and snooze enable (ZZ). There is also
a burst mode pin (MODE) that selects between inter-
leaved and linear burst modes. The data-out (Q), en-
abled by OE#, is also asynchronous. WRITE cycles can
be from one to two bytes wide (x18) or from one to four
bytes wide (x32/x36), as controlled by the write control
inputs.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) input pins. Subsequent burst addresses can be
internally generated as controlled by the burst advance
pin (ADV#).
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device,
BWa# controls DQa pins and DQPa; BWb# controls
DQb pins and DQPb. During WRITE cycles on the x32
and x36 devices, BWa# controls DQa pins and DQPa;
BWb# controls DQb pins and DQPb; BWc# controls
ww2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM
wMT58L128L18D_C.p65 – Rev. C, Pub. 11/02
1
©2002, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
1 page  
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36
PIPELINED, DCD SYNCBURST SRAM
TQFP PIN DESCRIPTIONS
x18
37
36
32-35, 44-49,
80-82, 99,
100
93
94
–
–
87
88
89
98
92
64
97
86
83
x32/x36
37
36
32-35, 44-49,
81, 82, 99,
100
93
94
95
96
87
88
89
98
92
64
97
86
83
SYMBOL
SA0
SA1
SA
BWa#
BWb#
BWc#
BWd#
BWE#
GW#
CLK
CE#
CE2#
ZZ
CE2
OE#
ADV#
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
DESCRIPTION
Synchronous Address Inputs: These inputs are registered and must
meet the setup and hold times around the rising edge of CLK.
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa pins and DQPa; BWb# controls DQb pins and
DQPb. For the x32 and x36 versions, BWa# controls DQa pins and
DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. Parity is only
available on the x18 and x36 versions.
Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the
rising edge of CLK.
Global Write: This active LOW input allows a full 18-, 32-, or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
Clock: This signal registers the address, data, chip enable, byte
write enables and burst control inputs on its rising edge. All
synchronous inputs must meet setup and hold times around the
clock’s rising edge.
Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after
the external address is loaded. A HIGH on this pin effectively causes
wait states to be generated (no address advance). To ensure use of
correct address during a WRITE cycle, ADV# must be HIGH at the
rising edge of the first clock after an ADSP# cycle is initiated.
(continued on next page)
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L128L18D_C.p65 – Rev. C, Pub. 11/02
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
5 Page 
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36
PIPELINED, DCD SYNCBURST SRAM
TQFP THERMAL RESISTANCE
DESCRIPTION
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Top of Case)
CONDITIONS
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51.
SYMBOL TYP
θJA 40
UNITS NOTES
°C/W 1
θJC 8 °C/W 1
NOTE: 1. This parameter is sampled.
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L128L18D_C.p65 – Rev. C, Pub. 11/02
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet MT58L64L36D.PDF ] | |
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