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PDF LC708728V Data sheet ( Hoja de datos )
| Número de pieza | LC708728V | |
| Descripción | High Performance 24-Bit D/A Converter Features | |
| Fabricantes | Sanyo Electric | |
| Logotipo |  |
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heet4U.comOrdering number : ENN7236
CMOS LSI
LC708728V
High-Performance 24-Bit 192 kHz D/A Converter Features
Built-in Electronic Volume Control and DSD Support
.DataSOverview
wwThe LC708728V is a high-performance stereo D/A
w converter developed for high-end audio applications such
Features
• Stereo D/A converter that supports both 24-bit PCM and
1-bit DSD
as DVD systems, home theater systems, and digital TV
sets. It supports 16 to 32-bit word length PCM data as its
digital input format, and supports sampling rates up to
m192 kHz. It can also be used in a DSD (Direct Stream
oDigital) compatible mode by supplying a 64-bit stream for
.ceach input channel.
This IC is formed from serial interface port, digital
interpolation filter, multi-bit ∑∆ converter, and stereo D/A
Uconverter functions. It includes muting and attenuator
circuits that can be controlled individually for each
t4channel.
The operating mode can be selected to be either software
econtrol mode or hardware control mode. In software
econtrol mode, the IC can be controlled by a
microcontroller over a 2-wire or 3-wire serial port. In this
hmode, a wide range of functions, including muting,
attenuation, and phase inversion can be controlled.
SDSD mode can only be used in hardware control mode.
taThis IC is optimal for use as an interface for AC-3, DTS,
and MPEG audio decoders for surround control, and for
ause in DVD players that support DVD-A.
• Signal-to-noise ratio: 106 dB (48 kHz, A weighted)
• Total harmonic distortion: –97 dB
• D/A converter sampling frequency: 8 kHz to 192 kHz
• Control modes: Either software or hardware mode can
be selected.
• Built-in microprocessor interface (either 2-wire or 3-
wire)
• Input data formats
I2S, left/right justified, DSP
16, 20, 24, and 32 bits
• Built-in electronic volume control with independent left
and right channel controls
0 to 127.5 dB in 0.5 dB steps
• Operating voltage range: 3.0 to 5.5 V
• Package: 20-pin SSOP
Applications
• DVD audio and DVD “universal” players
• Home theater systems
• Digital TVs
• Digital broadcast receivers
w.D• This LSI is designed and produced by Wolfson Microelectronics Ltd., and sold by SANYO Electric Co., Ltd.
wbased on corroboration between Wolfson Microelectronics Ltd. and SANYO Electric Co., Ltd.
w• CCB is the registered trademark of SANYO Electric Co., Ltd.
• CCB is the original bus format of SANYO Electric Co., Ltd. and all bus addresses are controlled by SANYO
mElectric Co., Ltd.
U.coAny and all SANYO products described or contained herein do not have specifications that can handle
t4applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
econtrol systems, or other applications whose failure can be reasonably expected to result in serious
ephysical and/or material damage. Consult with your SANYO representative nearest you before using
hany SANYO products described or contained herein in such applications.
SSANYO assumes no responsibility for equipment failures that result from using products at values that
taexceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
aherein.
SANYO Electric Co.,Ltd. SemiconductowrwC.oDmpanyTOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
w 52504TN (OT) No. 7236-1/31
1 page  
LC708728V
Absolute Maximum Ratings
The absolute maximum ratings given here are only stress ratings. This device may be permanently damaged if it is
operated continuously above any of these limits. Device function operating limits under the specified test conditions and
the guaranteed performance specifications are shown in the electrical characteristics.
ESD Sensitive Device. This device is fabricated in a CMOS process. As a result, it can be easily damaged
by excessive electrostatic voltages. Appropriate anti-static measures must be taken when handling or
storing this device.
Parameter
Digital system supply voltage
Analog system supply voltage
Digital input voltage range
Analog input voltage range
Master clock frequency
Operating temperature
Storage temperature
Maximum mounting temperature
(soldering time: 10 s)
Maximum mounting temperature
(soldering time: 2 m)
Symbol
Topr
Tstg
Conditions
min
–0.3
–0.3
DGND – 0.3
AGND – 0.3
–25
–65
Note: The potential difference between the analog system ground and the digital system ground must be 0.3 V or less.
Ratings
typ
max
+7
+7
DVDD + 0.3
AVDD + 0.3
50
+85
+150
+240
+183
Unit
V
V
V
V
MHz
°C
°C
°C
°C
Allowable Operating Ranges
Parameter
Symbol
Test Conditions
Digital system supply voltage
DVDD
Analog system supply voltage
AVDD
GND
AGND, DGND
Potential difference between DGND and AGND
Analog system supply current
AVDD = 5 V
Digital system supply current
DVDD = 5 V
Analog system supply current
AVDD = 3.3 V
Digital system supply current
DVDD = 3.3 V
min
3.0
3.0
–0.3
Ratings
typ
0
0
19
8
18
4
max
5.5
5.5
+0.3
Unit
V
V
V
V
mA
mA
mA
mA
Electrical Characteristics
Test conditions at Ta = 25°C, AVDD, DVDD = 5 V, AGND = 0 V, DGND = 0 V, fs = 48 kHz, MCLK = 256 fs (Unless otherwise specified.)
Parameter
[Digital Logic Levels (TTL levels)]
Low-level input voltage
High-level input voltage
Low-level output voltage
High-level output voltage
[Analog Reference Levels]
Reference voltage
Voltage divider resistance
Symbol
Test Conditions
VIL
VIH
VOL
VOH
IOL = 1 mA
IOH = 1 mA
VMID
RVMID
min
2.0
AVDD – 0.3 V
(VREFP –
VREFN) /
2 – 50 mV
Ratings
typ
(VREFP –
VREFN) / 2
12
Unit
max
0.8
AGND + 0.3 V
V
V
V
V
(VREFP –
VREFN) /
2 + 50 mV
V
kΩ
Continued on next page.
No. 7236-5/31
5 Page 
LC708728V
Test conditions at Ta = 25°C, AVDD, DVDD = 5 V, AGND = 0 V, DGND = 0 V, fs = 48 kHz, MCLK = 256 fs (Unless otherwise specified.)
Parameter
Symbol
Test Conditions
Ratings
Unit
min typ max
[Program Register Input]
SCKDSD pulse cycle time
SCKDSD pulse width (low)
SCKDSD pulse width (high)
Data setup time for the start signal from SDIDEM to SCKDSD
Data hold time for the start signal from SCKDSD to SDIDEM
Data setup time from SDIDEM to SCKDSD
Data hold time from SCKDSD to SDIDEM
SCKDSD rise time
SCKDSD fall time
SDIDEM rise time
SDIDEM fall time
Data setup time for the stop signal from SDIDEM to SCKDSD
tSCY
tSCL
tSCH
tSSU
tSHD
tDSU
tDHD
tSCR
tSCF
tDR
tDF
tESU
80 ns
20 ns
20 ns
10 ns
10 ns
20 ns
20 ns
5 ns
5 ns
5 ns
5 ns
10 ns
Notes: 1. The device address in 2-wire mode is 001101X (binary). The last bit can be selected by the user.
2. The CSBIWL pin indicates the last bit of the chip address in 2-wire interface mode.
3. When using 2-wire mode, we recommend that the LATI2S pin be connected to either DGND or DVSS to prevent the interface from being switched to
3-wire mode by noise.
No. 7236-11/31
11 Page | ||
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| PDF Descargar | [ Datasheet LC708728V.PDF ] | |
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