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MC74AC161 の電気的特性と機能

MC74AC161のメーカーはON Semiconductorです、この部品の機能は「Synchronous Presettable Binary Counter」です。


製品の詳細 ( Datasheet PDF )

部品番号 MC74AC161
部品説明 Synchronous Presettable Binary Counter
メーカ ON Semiconductor
ロゴ ON Semiconductor ロゴ 




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MC74AC161 Datasheet, MC74AC161 PDF,ピン配置, 機能
MC74AC161, MC74ACT161,
MC74AC163, MC74ACT163
Synchronous Presettable
Binary Counter
The MC74AC161/74ACT161 and MC74AC163/74ACT163 are
high−speed synchronous modulo−16 binary counters. They are
synchronously presettable for application in programmable dividers
and have two types of Count Enable inputs plus a Terminal Count
output for versatility in forming synchronous multistage counters.
The MC74AC161/74ACT161 has an asynchronous Master Reset
input that overrides all other inputs and forces the outputs LOW. The
MC74AC163/74ACT163 has a Synchronous Reset input that
overrides counting and parallel loading and allows the outputs to be
simultaneously reset on the rising edge of the clock.
Features
Synchronous Counting and Loading
High−Speed Synchronous Expansion
Typical Count Rate of 125 MHz
Outputs Source/Sink 24 mA
ACT161 and ACT163 Have TTL Compatible Inputs
These are Pb−Free Devices
VCC TC Q0 Q1 Q2 Q3 CET PE
16 15 14 13 12 11 10 9
www.onsemi.com
16
1
xxx
y
A
WL
Y
WW
G
MARKING
DIAGRAM
16
SOIC−16
D SUFFIX
CASE 751B
1
xxx16yG
AWLYWW
= AC or ACT
= 1 or 3
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
12345678
*R CP P0 P1 P2 P3 CEP GND
Figure 1. Pinout: 16−Lead Packages Conductors
(Top View)
PIN ASSIGNMENT
PIN FUNCTION
CEP
Count Enable Parallel Input
CET
Count Enable Trickle Input
CP Clock Pulse Input
MR (161) Asynchronous Master Reset Input
SR (163) Synchronous Reset Input
P0−P3
PE
Parallel Data Inputs
Parallel Enable Input
Q0−Q3
TC
Flip−Flop Outputs
Terminal Count Output
© Semiconductor Components Industries, LLC, 2015
January, 2015 − Rev. 8
1
Publication Order Number:
MC74AC161/D

1 Page





MC74AC161 pdf, ピン配列
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
PE
161 163
CEP
CET 163
ONLY
P0 P1 P2
P3
TC
CP
CP 161
CP
ONLY
D CP D
CD Q Q
Q0 Q0
DETAIL A
DETAIL A
DETAIL A
DETAIL A
MR 161
SR 163
NOTE:
Q0 Q1 Q2
This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Figure 4. Logic Diagram
Q3
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
VI
VO
IIK
IOK
IO
ICC
IGND
TSTG
TL
TJ
qJA
PD
MSL
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Sink/Source Current
DC Supply Current per Output Pin
DC Ground Current per Output Pin
Storage Temperature Range
Lead temperature, 1 mm from Case for 10 Seconds
Junction temperature under Bias
Thermal Resistance (Note 2)
Power Dissipation in Still Air at 65°C (Note 3)
Moisture Sensitivity
(Note 1)
*0.5 to )7.0
*0.5 v VI v VCC )0.5
*0.5 v VO v VCC )0.5
$20
$50
$50
$50
$50
*65 to )150
260
)150
69.1
500
Level 1
V
V
V
mA
mA
mA
mA
mA
°C
°C
°C
°C/W
mW
FR
VESD
Flammability Rating
ESD Withstand Voltage
Oxygen Index: 30% − 35%
Human Body Model (Note 4)
Machine Model (Note 5)
Charged Device Model (Note 6)
UL 94 V−0 @ 0.125 in
> 2000
> 200
> 1000
V
ILatch−Up Latch−Up Performance Above VCC and Below GND at 85°C (Note 7)
$100
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. IO absolute maximum rating must be observed.
2. The package thermal impedance is calculated in accordance with JESD51−7.
3. 500 mW at 65°C; derate to 300 mW by 10 mW/ from 65°C to 85°C.
4. Tested to EIA/JESD22−A114−A.
5. Tested to EIA/JESD22−A115−A.
6. Tested to JESD22−C101−A.
7. Tested to EIA/JESD78.
www.onsemi.com
3


3Pages


MC74AC161 電子部品, 半導体
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
AC OPERATING REQUIREMENTS
Symbol
Parameter
Setup Time, HIGH or LOW
ts Pn to CP
Hold Time, HIGH or LOW
th Pn to CP
Setup Time, HIGH or LOW
ts PE to CP
Hold Time, HIGH or LOW
th PE to CP
Setup Time, HIGH or LOW
ts CEP or CET to CP
Hold Time, HIGH or LOW
th CEP or CET to CP
Clock Pulse Width (Load)
tw HIGH or LOW
Clock Pulse Width (Count)
tw HIGH or LOW
tw MR Pulse Width, LOW
Recovery TIme
trec MR to CP
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
74AC161
74AC161
VCC*
(V)
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Typ Guaranteed Minimum
Unit
Fig.
No.
3.3 6.0
5.0 3.5
13.5
8.5
16.0
10.5 ns 3−9
3.3 −7.0
5.0 −4.0
−1.0
0
−0.5
0 ns 3−9
3.3 6.5
5.0 4.0
11.5
7.5
14.0
8.5 ns 3−9
3.3 −6.0
5.0 −3.5
0
0.5
0
1.0 ns 3−9
3.3 3.0
5.0 2.0
6.0
4.5
7.0
5.0 ns 3−9
3.3 −3.5
5.0 −2.0
0
0
0
0.5 ns 3−9
3.3 2.0
5.0 2.0
3.5
2.5
4.0
3.0 ns 3−6
3.3 2.0
5.0 2.0
4.0
3.0
4.5
3.5 ns 3−6
3.3 3.0
5.0 2.5
5.5
4.5
7.5
6.0 ns 3−6
3.3 −2.0
5.0 −1.0
−0.5
0
0
0.5 ns 3−9
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6

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部品番号部品説明メーカ
MC74AC161

Synchronous Presettable Binary Counter

ON Semiconductor
ON Semiconductor
MC74AC163

Synchronous Presettable Binary Counter

ON Semiconductor
ON Semiconductor


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