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Número de pieza | NB6L11 | |
Descripción | 2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL | |
Fabricantes | ON Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de NB6L11 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
No Preview Available ! NB6L11
2.5V/3.3V Multilevel Input to
Differential LVPECL/LVNECL
1:2 Clock or Data
Fanout Buffer/Translator
The NB6L11 is an enhanced differential 1:2 clock or data fanout
buffer/translator. The device has the same pinout and is functionally
equivalent to the LVEL11, EP11, LVEP11 devices. Moreover, the
device is optimized for the systems that require LOW skew, LOW
jitter and LOW power consumption.
Differential input can be configured to accept single−ended signal
by applying an external reference voltage to unused complimentary
input pin. Input accept LVNECL, LVPECL, LVTTL, LVCMOS,
CML, or LVDS. The outputs are 800 mV ECL signals.
• Maximum Input Clock Frequency w 6 GHz Typical
• Maximum Input Data Rate w 6 Gb/s Typical
• Low 14 mA Typical Power Supply Current
• 150 ps Typical Propagation Delay
• 5 ps Typical Within Device Skew
• 75 ps Typical Rise/Fall Times
• PECL Mode Operating Range: VCC = 2.375 V to 3.465 V
with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V
with VEE = −2.375 V to −3.465 V
• Open Input Default State
• Q Outputs Will Default LOW with Inputs Open or at VEE
• LVDS, LVPECL, LVNECL, LCMOS, LVTTL and CML Input
Compatible
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8
1
SO−8
D SUFFIX
CASE 751
MARKING DIAGRAMS*
8
6L11
ALYW
1
8
1
TSSOP−8
DT SUFFIX
CASE 948R
8
6L11
ALYW
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
Package Shipping†
NB6L11D
SO−8 98 Units/Rail
NB6L11DR2
SO−8
2500/
Tape & Reel
NB6L11DT**
TSSOP−8 100 Units/Rail
NB6L11DTR2**
TSSOP−8
2500/
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
**Future Product − Contact factory for availability.
Semiconductor Components Industries, LLC, 2004
April, 2004 − Rev. 2
1
Publication Order Number:
NB6L11/D
1 page NB6L11
Table 5. DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 9)
−40°C
25°C
85°C
Symbol
Characteristic
Min Typ
IEE Negative Power Supply Current (Note 10) 5 14
VOH Output HIGH Voltage (Note 11)
2150 2250
VOL Output LOW Voltage (Note 11)
1430 1550
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 10, 12)
Max
20
2350
1670
Min
5
2200
1480
Typ Max
14 20
2300 2400
1600 1720
Min
5
2250
1530
Typ
14
2350
1650
Max
20
2450
1770
Unit
mA
mV
mV
Vth Input Threshold Reference Voltage Range 1125
(Note 7)
VCC 1125
−75
VCC 1125
−75
VCC mV
−75
VIH Single−Ended Input HIGH Voltage
Vth
VCC
Vth
VCC
Vth
VCC mV
+75 +75 +75
VIL Single−Ended Input LOW Voltage VEE Vth VEE Vth VEE Vth mV
−75 −75 −75
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 11, 13)
VIHD
VILD
Differential Input HIGH Voltage
Differential Input LOW Voltage
1200
VEE
VCC
VCC
−75
1200
VEE
VCC
VCC
−75
1200
VEE
VCC mV
VCC mV
−75
VCMR
Input Common Mode Range
1163
(Differential Cross−Point Voltage) (Note 8)
VCC 1163
−38
VCC 1163
−38
VCC mV
−38
VID Differential Input Voltage (VIHD − VILD)
75
2500 75
2500 75
2500 mV
IIH Input HIGH Current
D 50 150
D 10 150
50 150
10 150
50 150 mA
10 150
IIL Input LOW Current
D −150 −5
D −150 −30
−150 −5
−150 −30
−150 −5
−150 −30
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
7. Vth is applied to the complementary input when operating in single−ended mode.
8. VCMR minimum varies 1:1 with VEE, VCMR maximum varies 1:1 with VCC.
9. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.
10. All input and output pins left open.
11. All loading with 50 W to VCC − 2.0 V.
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5
5 Page NB6L11
PACKAGE DIMENSIONS
−X−
A
SOIC−8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751−07
ISSUE AB
B
−Y−
−Z−
H
85
S 0.25 (0.010) M Y M
1
4
K
G
D
C
SEATING
PLANE
N X 45 _
0.10 (0.004)
M
0.25 (0.010) M Z Y S X S
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0_ 8_ 0_ 8_
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
7.0
0.275
1.52
0.060
4.0
0.155
0.6
0.024
SO−8
1.270
0.050
ǒ ǓSCALE 6:1
mm
inches
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11
11 Page |
Páginas | Total 12 Páginas | |
PDF Descargar | [ Datasheet NB6L11.PDF ] |
Número de pieza | Descripción | Fabricantes |
NB6L11 | 2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL | ON Semiconductor |
NB6L11M | Differential CML Fanout Buffer | ON Semiconductor |
NB6L11S | Input to LVDS Fanout Buffer / Translator | ON Semiconductor |
NB6L14 | Differential 1:4 LVPECL Fanout Buffer | ON Semiconductor |
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