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PDF TSC80251G2D Data sheet ( Hoja de datos )
| Número de pieza | TSC80251G2D | |
| Descripción | 8/16-bit Microcontroller with Serial Communication Interfaces | |
| Fabricantes | TEMIC Semiconductors | |
| Logotipo |  |
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TSC80251G2D
8/16-bit Microcontroller with Serial Communication
Interfaces
1. Description
The TSC80251G2D products are derivatives of the
TEMIC Microcontroller family based on the 8/16-bit
C251 Architecture. This family of products is tailored
to 8/16-bit microcontroller applications requiring an
increased instruction throughput, a reduced operating
frequency or a larger addressable memory space. The
architecture can provide a significant code size reduction
when compiling C programs while fully preserving the
legacy of C51 assembly routines.
The TSC80251G2D derivatives are pin and software
compatible with standard 80C51/Fx/Rx/Rx+ with
extended on-chip data memory (1 Kbyte RAM) and up
to 256 Kbytes of external code and data. Additionally,
the TSC83251G2D and TSC87251G2D provide on-chip
code memory: 32 Kbytes ROM and 32 Kbytes EPROM/
OTPROM respectively.
They provide transparent enhancements to Intel’s
8xC251Sx family with an additional Synchronous Serial
Link Controller (SSLC supporting I2C, µWire and SPI
protocols), a Keyboard interrupt interface, a dedicated
Baud Rate Generator for UART, and Power Management
features.
TSC80251G2D derivatives are optimized for speed and
for low power consumption on a wide voltage range.
Note:
This Datasheet provides the technical description of the TSC80251G2D derivatives. For further information on the device usage, please request
the TSC80251 Programmer’s Guide and the TSC80251G1D Design Guide.
2. Typical Applications
q ISDN Terminals
q High-Speed Modems
q PABX (SOHO)
q Line Cards
q DVD ROM and Players
q Printers
q Plotters
q Scanners
q Banking Machines
q Barcode Readers
q Smart Cards Readers
q High-End Digital Monitors
q High-End Joysticks
Rev. A - May 7, 1999
1
1 page  
TSC80251G2D
P1.5/CEX2/MISO
P1.6/CEX3/SCL/SCK/WAIT#
P1.7/A17/CEX4/SDA/MOSI/WCLK
RST
P3.0/RXD
AWAIT#
P3.1/TXD
P3.2/INT0#
P3.3/INT1#
P3.4/T0
P3.5/T1
1
2
3
4
5
6
7
8
9
10
11
TSC80251G2D
33 P0.4/AD4
32 P0.5/AD5
31 P0.6/AD6
30 P0.7/AD7
29 EA#/VPP
28 NMI
27 ALE/PROG#
26 PSEN#
25 P2.7/A15
24 P2.6/A14
23 P2.5/A13
Figure 4. TSC80251G2D 44-pin VQFP Package
Table 1. TSC80251G2D Pin Assignment
DIP PLCC VQFP
Name
1 39 VSS1
1 2 40 P1.0/T2
2 3 41 P1.1/T2EX
3 4 42 P1.2/ECI
4 5 43 P1.3/CEX0
5 6 44 P1.4/CEX1/SS#
6 7 1 P1.5/CEX2/MISO
7 8 2 P1.6/CEX3/SCL/SCK/WAIT#
8 9 3 P1.7/A17/CEX4/SDA/MOSI/WCLK
9 10 4 RST
10 11
5 P3.0/RXD
12 6 AWAIT#
11 13
7 P3.1/TXD
12 14
8 P3.2/INT0#
13 15
9 P3.3/INT1#
14 16 10 P3.4/T0
15 17 11 P3.5/T1
16 18 12 P3.6/WR#
17 19 13 P3.7/A16/RD#
18 20 14 XTAL2
19 21 15 XTAL1
20 22 16 VSS
DIP PLCC VQFP
Name
23 17 VSS2
21 24 18 P2.0/A8
22 25 19 P2.1/A9
23 26 20 P2.2/A10
24 27 21 P2.3/A11
25 28 22 P2.4/A12
26 29 23 P2.5/A13
27 30 24 P2.6/A14
28 31 25 P2.7/A15
29 32 26 PSEN#
30 33 27 ALE/PROG#
34 28 NMI
31 35 29 EA#/VPP
32 36 30 P0.7/AD7
33 37 31 P0.6/AD6
34 38 32 P0.5/AD5
35 39 33 P0.4/AD4
36 40 34 P0.3/AD3
37 41 35 P0.2/AD2
38 42 36 P0.1/AD1
39 43 37 P0.0/AD0
40 44 38 VDD
Rev. A - May 7, 1999
5
5 Page 
TSC80251G2D
Table 3. C251 Core SFRs
Mnemonic
ACC(1)
B(1)
PSW
PSW1
SP(1)
Name
Accumulator
B Register
Program Status Word
Program Status Word 1
Stack Pointer - LSB of SPX
Mnemonic
SPH(1)
DPL(1)
DPH(1)
DPXL(1)
Name
Stack Pointer High - MSB of SPX
Data Pointer Low byte - LSB of DPTR
Data Pointer High byte - MSB of DPTR
Data Pointer Extended Low byte of DPX - Region
number
Note:
1. These SFRs can also be accessed by their corresponding registers in the register file.
Table 4. I/O Port SFRs
Mnemonic Name
P0 Port 0
P1 Port 1
Mnemonic Name
P2 Port 2
P3 Port 3
Mnemonic Name
TL0 Timer/Counter 0 Low Byte
TH0 Timer/Counter 0 High Byte
TL1 Timer/Counter 1 Low Byte
TH1 Timer/Counter 1 High Byte
TL2 Timer/Counter 2 Low Byte
TH2 Timer/Counter 2 High Byte
TCON
Timer/Counter 0 and 1 Control
Table 5. Timers SFRs
Mnemonic Name
TMOD
Timer/Counter 0 and 1 Modes
T2CON
Timer/Counter 2 Control
T2MOD
Timer/Counter 2 Mode
RCAP2L
Timer/Counter 2 Reload/Capture Low Byte
RCAP2H Timer/Counter 2 Reload/Capture High Byte
WDTRST WatchDog Timer Reset
Mnemonic Name
SCON
Serial Control
SBUF
Serial Data Buffer
SADEN
Slave Address Mask
Table 6. Serial I/O Port SFRs
Mnemonic Name
SADDR
Slave Address
BRL Baud Rate Reload
BDRCON Baud Rate Control
Table 7. SSLC SFRs
Mnemonic Name
SSCON
Synchronous Serial control
SSDAT
Synchronous Serial Data
SSCS
Synchronous Serial Control and Status
Mnemonic Name
SSADR
Synchronous Serial Address
SSBR
Synchronous Serial Bit Rate
Rev. A - May 7, 1999
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TSC80251G2D.PDF ] | |
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