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ST93C06C の電気的特性と機能

ST93C06CのメーカーはST Microelectronicsです、この部品の機能は「256 bit 16 x 16 or 32 x 8 SERIAL MICROWIRE EEPROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 ST93C06C
部品説明 256 bit 16 x 16 or 32 x 8 SERIAL MICROWIRE EEPROM
メーカ ST Microelectronics
ロゴ ST Microelectronics ロゴ 




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ST93C06C Datasheet, ST93C06C PDF,ピン配置, 機能
ST93C06
ST93C06C
256 bit (16 x 16 or 32 x 8) SERIAL MICROWIRE EEPROM
NOT FOR NEW DESIGN
1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DATA RETENTION
DUAL ORGANIZATION: 16 x 16 or 32 x 8
BYTE/WORD and ENTIRE MEMORY
PROGRAMMING INSTRUCTIONS
SELF-TIMED PROGRAMMING CYCLE with
AUTO-ERASE
READY/BUSY SIGNAL DURING
PROGRAMMING
SINGLE 5V ±10% SUPPLY VOLTAGE
SEQUENTIAL READ OPERATION
5ms TYPICAL PROGRAMMING TIME
ENHANCED ESD/LATCH UP
PERFORMANCES for ”C” VERSION
ST93C06 and ST93C06C are replaced by
the M93C06
8
1
PSDIP8 (B)
0.4mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
DESCRIPTION
The ST93C06 and ST93C06C are 256 bit Electri-
cally Erasable Programmable Memory (EEPROM)
fabricated with SGS-THOMSON’s High Endurance
Single Polysilicon CMOS technology. In the text the
two products are referred to as ST93C06.
The memory is divided into either 32 x 8 bit bytes
or 16 x 16 bit words. The organization may be
selected by a signal applied on the ORG input.
The memory is accessed through a serial input (D)
and by a set of instructions which includes Read a
byte/word, Write a byte/word, Erase a byte/word,
Erase All and Write All. ARead instruction loads the
address of the first byte/word to be read into an
internal address pointer.
Table 1. Signal Names
S Chip Select Input
D Serial Data Input
Q Serial Data Output
C Serial Clock
ORG
Organisation Select
VCC Supply Voltage
VSS Ground
D
C
S
ORG
VCC
ST93C06
ST93C06C
VSS
Q
AI00816B
June 1997
This is information on a product still in production bu t not recommended for new de signs.
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1 Page





ST93C06C pdf, ピン配列
ST93C06, ST93C06C
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Input Timing Reference Voltages
Output Timing Reference Voltages
20ns
0.4V to 2.4V
1V to 2.0V
0.8V to 2.0V
Note that Output Hi-Z is defined as the point where data
is no longer driven.
Figure 3. AC Testing Input Output Waveforms
2.4V
0.4V
2V
1V
INPUT
OUTPUT
2.0V
0.8V
AI00815
Table 3. Capacitance (1)
(TA = 25 °C, f = 1 MHz )
Symbol
Parameter
CIN Input Capacitance
COUT
Output Capacitance
Note: 1. Sampled only, not 100% tested.
Test Condition
VIN = 0V
VOUT = 0V
Min Max Unit
5 pF
5 pF
Table 4. DC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 5V ± 10%)
Symbol
Parameter
Test Condition
ILI Input Leakage Current
0V VIN VCC
ILO Output Leakage Current
0V VOUT VCC,
Q in Hi-Z
Supply Current (TTL Inputs)
ICC
Supply Current (CMOS Inputs)
S = VIH, f = 1 MHz
S = VIH, f = 1 MHz
ICC1 Supply Current (Standby)
S = VSS, C = VSS,
ORG = VSS or VCC
VIL Input Low Voltage (D, C, S)
VIH Input High Voltage (D, C, S)
VOL Output Low Voltage
IOL = 2.1mA
IOL = 10 µA
VOH Output High Voltage
IOH = –400µA
IOH = –10µA
Min
–0.3
2
2.4
VCC – 0.2
Max
±2.5
±2.5
3
2
50
0.8
VCC + 1
0.4
0.2
Unit
µA
µA
mA
mA
µA
V
V
V
V
V
V
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3Pages


ST93C06C 電子部品, 半導体
ST93C06, ST93C06C
POWER-ON DATA PROTECTION
In order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit resets all internal programming
circuitry and sets the device in the Write Disable
mode. When VCC reaches its functional value, the
device is properlyreset (in the Write Disable mode)
and is ready to decode and execute an incoming
instruction. A stable VCC must be applied before
any logic signal.
INSTRUCTIONS
The ST93C06 has seven instructions, as shown in
Table 6. The op-codes of the instructions are made
up of 4 bits: some instructions use only the first two
bits, others use all four bits to define the op-code.
The op-code is followed by an address for the
byte/word which is four bits long for the x16 organi-
zation or five bits long for the x8 organization.
Each instruction is preceded by the rising edge of
the signal applied on the S input (assuming that
clock C and data input D are low), followed by a
first clock pulse which is ignored by the ST93C06
(optional clock pulse for the ST93C06C). The data
input D is then sampled upon the following rising
edges of the clock C untill a ’1’ is sampled and
decoded by the ST93C06 as a Start bit. Even
though the first clock pulse is ignored, it recom-
mended to pull low the data input D during this first
clock pulse in order to keep the timing upwardly
compatible with other ST93Cxx devices.
The ST93C06 is fabricated in CMOS technology
and is therefore able to run from zero Hz (static
input signals) up to the maximum ratings (specified
in Table 5).
Read
The Read instruction (READ) outputs serial data
on the Data Output (Q). When a READ instruction
is received, the instruction and address are de-
coded and the data from the memory is transferred
into an output shiftregister. A dummy ’0’ bit is output
first followed by the 8 bit byte or the 16 bit word with
the MSB first. Output data changes are triggered
by the Low to High transition of the Clock (C). The
ST93C06 will automatically increment the address
and will clock out the next byte/word as long as the
Chip Select input (S) is held High. In this case the
dummy ’0’ bit is NOT output between bytes/words
and a continuous stream of data can be read.
Erase/Write Enable and Disable
The Erase/Write Enable instruction (EWEN)
authorizesthe following Erase/Write instructions to
be executed, the Erase/Write Disable instruction
(EWDS) disables the execution of the following
Erase/Write instructions. When power is first ap-
plied, the ST93C06 enters the Disable mode.
When the Erase/Write Enable instruction (EWEN)
is executed, Write instructions remain enabled until
an Erase/Write Disable instruction (EWDS) is exe-
cuted or if the Power-on reset circuit becomes
active due to a reduced VCC. To protect the memory
contents from accidental corruption, it is advisable
to issue the EWDS instruction after every write
cycle. The READ instruction is not affected by the
EWEN or EWDS instructions.
Erase
The Erase instruction (ERASE) programs the ad-
dressed memory byte or word bits to ’1’. Once the
address is correctly decoded, the falling edge of the
Chip Select input (S) triggers a self-timed erase
cycle.
Table 6. Instruction Set
Instruction
Description
READ
Read Data from Memory
WRITE
Write Data to Memory
EWEN
Erase/Write Enable
EWDS
Erase/Write Disable
ERASE
Erase Byte or Word
ERAL
Erase All Memory
WRAL
Write All Memory
with same Data
Note: X = don’t care bit.
Op-Code
10XX
01XX
0011
0000
11XX
0010
0001
x8 Org
Address
(ORG = 0)
A4-A0
A4-A0
XXXXX
XXXXX
A4-A0
XXXXX
XXXXX
Data
Q7-Q0
D7-D0
D7-D0
x16 Org
Address
(ORG = 1)
A3-A0
A3-A0
XXXX
XXXX
A3-A0
XXXX
XXXX
Data
Q15-Q0
D15-D0
D15-D0
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6 Page



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部品番号部品説明メーカ
ST93C06

256 bit 16 x 16 or 32 x 8 SERIAL MICROWIRE EEPROM

ST Microelectronics
ST Microelectronics
ST93C06C

256 bit 16 x 16 or 32 x 8 SERIAL MICROWIRE EEPROM

ST Microelectronics
ST Microelectronics


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